am335x can't read uboot.img from mmc0

hi biser gatchev, thanks for your answer. i performed DDR3 initialization as described in http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips and http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling.but to configuration for DDR3 using software leveling, the timing of the DDR3 that i couldn't to determine. l paste the macro of DDR3 and my ddr3 datasheet. thanks.my ddr3 is h5tq4g63mfr-h9c 512M.

/* AM335X EMIF Register values */
#ifdef CONFIG_AM335X
#define DDR2_EMIF_SDMGT        0x80000000
#define EMIF_SDRAM        0x00004650
//#define EMIF_PHYCFG        0x2
#define DDR_PHY_RESET        (0x1 << 10)
#define DDR_FUNCTIONAL_MODE_EN    0x1
#define DDR_PHY_READY        (0x1 << 2)
#define    VTP_CTRL_READY        (0x1 << 5)
#define VTP_CTRL_ENABLE        (0x1 << 6)
#define VTP_CTRL_LOCK_EN    (0x1 << 4)
#define VTP_CTRL_START_EN    (0x1)
#define DDR2_RATIO        0x80    /* for mDDR */
#define DDR2_CMD_FORCE        0x00    /* common #def */
#define DDR2_CMD_DELAY        0x00
#define DDR3_RATIO        0x100/*0x40 add by huang*/
#define DDR3_CMD_FORCE        0x00
#define DDR3_CMD_DELAY        0x00
#define DDR2_EMIF_READ_LATENCY    0x100005    /* Enable Dynamic Power Down */
#define DDR2_EMIF_TIM1        0x0666B3C9
#define DDR2_EMIF_TIM2        0x243631CA
#define DDR2_EMIF_TIM3        0x0000033F
#define DDR2_EMIF_SDCFG        0x41805332
#define DDR2_EMIF_SDREF1    0x00004650
#define DDR2_EMIF_SDREF2    0x0000081a
#define DDR2_DLL_LOCK_DIFF    0x0
#define DDR2_RD_DQS        0x12
#define DDR2_PHY_FIFO_WE    0x80
#define DDR3_EMIF_READ_LATENCY    0x0000010B/*0x06 add by huang*/
#define DDR3_EMIF_TIM1        0x0CCCE524/*0x0888A39B add by huang*/
#define DDR3_EMIF_TIM2        0x30308023/*0x26337FDA add by huang*/
#define    DDR3_EMIF_TIM3        0x009F82CF/*0x501F830F8 add by huang*/
#define DDR3_EMIF_SDCFG        0x61C04B32/*0x61C04AB2 add by huang*/
#define DDR3_EMIF_SDREF        0x10000C30/*0x0000093B add by huang*/
#define DDR3_ZQ_CFG        0x62A45032/*0x50074BE4 add by huang*/
#define DDR3_DLL_LOCK_DIFF    0xF/*0x1 add by huang*/
#define DDR3_RD_DQS        0x3B
#define DDR3_PHY_FIFO_WE    0x12A/*0x100*/
#define    DDR2_INVERT_CLKOUT    0x00
#define    DDR2_WR_DQS        0x00
#define    DDR2_PHY_WRLVL        0x00
#define    DDR2_PHY_GATELVL    0x00
#define    DDR2_PHY_WR_DATA    0x40
#define    DDR2_PHY_RANK0_DELAY    0x01
#define DDR2_PHY_DLL_LOCK_DIFF    0x0
#define DDR2_IOCTRL_VALUE    0x18B
#define DDR3_INVERT_CLKOUT    0x1
#define DDR3_WR_DQS        0xA6/*0x85 add by huang*/
#define DDR3_PHY_WRLVL        0x20/*0x00 add by huang*/
#define DDR3_PHY_GATELVL    0x20/*0x00 add by huang*/
#define DDR3_PHY_WR_DATA    0xE6/*0xC1 add by huang*/
#define    DDR3_PHY_RANK0_DELAY    0x01
#define DDR3_PHY_DLL_LOCK_DIFF    0x0
#define DDR3_IOCTRL_VALUE    0x18B
#define EMIF_RDWR_LVL_VALUE    0x80000000
#endif

1663.H5TQ4G63MFR-H9C-Hynix.pdf

Hi Biser Gatchev-XID, i dowload the tool before i post the question. ashamed,i couldn't find all parameters from my ddr3 datasheet that flaged by the yellow district of the tool. so i couldn't determine the timing. would you help me to determine it ? the timing of the last post is modified with other project which use the ddr3 .

by the way ,i don't know if somewhere else to modify except http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling and  http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips#DDR_PHY_Registers?

Hi Biser Gatchev-XID, thanks very much for your help, using the timing you sent to me,my board can go to the kernel.although there are some error in my kernel.it would a big step to my development.grateful to you!

Dear Jery, I'm using same as your solution & DDR3. But my code can't run to "reading u-boot.img". Would you provide your setting for my reference & test?? I need ddr_defs.h & evm.c if you would like share with me. Thanks a lot~