we have a unusual issue with the am3359 processor, where there is unexplained interaction between NAND flash access and Ethernet. The effect of this is that Ethernet is dead unless we don't boot from NAND.
Below is the description of the issue, as far as I can tell at the moment.
We are attempting to use the processor with an RMII Ethernet PHY.
We have an external reference clock, so pin 'RMII1_REF_CLK' is configured for mux mode 0 and bits 6 & 7 in MAC_MII_SEL are set to configure for an external 50MHz clock.
It turns out that despite all this, the pin doesn't act like a pure input pad. Specifically, in certain situations, the external clock signal appears to be subject to an unexpected load, depressing the 3.3V clock to about 2V
This is different from e.g. forcibly driving the pin low via GPIO in muxmode 7, where the external clock is down to under 1V.
The unexpected behaviour appears to be related to NAND flash access, even though the pin in question has no NAND related functionality.
Specifically, if the rom-boot code accesses the NAND flash first, an U-Boot loaded via X-Modem fails to receive a valid RMII clock. If the boot mode is set to try X-Modem first, everything is OK, unless the boot code is left to cycle through NAND access.
This can also be observed while issuing a NAND read command from the U-Boot command line, where the clock is released back to 3.3V in short 240ns pulses, between gaps of about 680ns where the clock is stuck at about 2V.
Is it possible that the whole I/O bank is internally switched to a different supply voltage, such that our input is clamped to 1.8V? Our PHY is 3.3V and we have VDDSHV5 set to 3.3V, but our NAND is operating at 1.8V
