Hello everybody.
I have an issue I can’t understand.
First I’m using the following tools & software:
Omapl 138 EVM board – Code Composer V5.3 – Psp bios V3.00.01 Cslr SPI Example
Using J13 to monitor SPI0 signals (SPI0_Clk, SPI0_SOMI and SPI0_SIMO) on oscilloscope.
I can run the Cslr SPI example without any problems and I can see what I send (as example configures SPI0 in Loopback mode)
1- The problem is that the SPI0 Clock is always as shown (when power the board up , before and after transmit data from SPIDAT1) in Pic (Even if disabling Loopback mode)
Where D0 => SPI0_Clk
D1 => SPI0_SOMI
D2 => SPI0_SIMO
2- When I tried to use SPI0 in normal mode (Loopback mode disabled) the same issue still exists
Is there something is missing in the configuration of SPI 0 instance?
Note:
I have already tried the same example with SPI1 with having no problems (SPI1_Clk, SOMI and SIMO works fine).
SPI project is attached with Loopback mode disabled for SPI0.
