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C6678 siliconversion 2.0 SRIO Problem

Mahendra varman
Intellectual 500 points

Hi

Our custom board has 2  C6678 dsp ( DSP1-- C6678 silicon version 1.0  &  DSP2 -- C6678 silicon version 2.0) on the same board.

Both Dsp's are connected to SRIO Switch.

DSP1 of silicon version 1.0 got trained with switch ( port ok , NO Input output error stopped state)...able to transfer srio data thru switch

DSP2 of silicon version 2.0 has issue.

SRIO Loopback is working in DSP2.

But when enabled Normal Operation in DSP2 after training with switch shows Port Ok but Input and output error stopped state is set.

Code used is DIOISR . Its working for DSP1 but DSP2 shows above issue.

We have used Same SRIO Clock source for DSP1 & DSP2..

Please suggest

  • 0
    TI__Mastermind 30825 points

    Have you tested this on more than one board and observed the same issue?

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Intellectual 500 points

    Hi

    Unfortunately we manufactured only one board.

    We would like to know whether silicon revision changes causes the issue  I/O error stopped state for DSP v 2.0 but not for DSP v 1.0  what we are facing in our board

    Thanks

  • 0 in reply to Mahendra varman
    TI__Mastermind 30825 points

    Mahendra,

    No, there are no such known issues on PG2.0. 

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Mastermind 6325 points

    Mahendra,

     

    Are you certian the ACKIDs are aligned for the second DSP?  Have you checked that you set up the routing table properly in the switch for both DSPs?  Have you checked that speed is configured correctly for each port on the switch and DSP? 

    Did you use the loopback mode on DSP2 that went through the switch and back to the DSP or just internal loop back mode?

    The tough part about switches is each port must be configured individually, so just becuase you did it correctly for DSP1 doesn't mean DSP2 was automatically set up.

    Brandy

  • 0 in reply to Brandy Jabkiewicz
    TI__Mastermind 23525 points

    Brandy is correct, each set of link partners is unique.  There is a software sequence to exit the error states and align ackids (if necessary), it is best to run this sequence on one of the link partners in all cases.  You can find reference to this in the following thread... http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/170264/752157.aspx#752157

    Regards,

    Travis

  • 0 in reply to tscheck
    Intellectual 500 points

    Hi Brandy and Tscheck

    My Test code and setup as follows

    DSP - C6678 , SRIO switch - CPS1432 . one freescale processor

    One Port of SRIO switch is connected to DSP1 1.0 and another port of srio switch is connected to DSP2 2.0.One another port of switch is connected to a freescale processor.

    ======

    DSP1- 1.0 silicon version

    =======

     1. Not initializing the SRIO switch registers ( meaning all register values has poweron default values).

     2. Took DIOISR code, changed to Normal Mode, Adjusted the PLL value for 1.25Gbaud.

    3. Loaded the code and ran the code. Checked Port Error status -- Port_ok bit is set, NO I/O stopped error state.

    4. Now Initialized CPS1432 switch with routing table of DSP1, Port Enable bit is set in switch

    5.  DATA transfer through the switch to freescale processor is successful

    ======

    DSP2- 2.0 silicon version

    =======

     1. Not initializing the SRIO switch registers ( meaning all register values has poweron default values).

     2. Took DIOISR code, changed to Normal Mode, Adjusted the PLL value for 1.25Gbaud.

    3. Loaded the code and ran the code. Checked Port Error status -- Port_ok bit is set, BUT I/O ERROR STOPPED STATE IS SET

    4. Now Initialized CPS1432 switch with routing table of DSP2, Port Enable bit is set in switch

    5.  DATA transfer through the switch to freescale processor GOT FAILED

    Please suggest

    Thanks

  • 0 in reply to Mahendra varman
    TI__Mastermind 23525 points

    You need to run the software error recovery process as step 3.5.  You can run it regardless of v1.1 or 2.0 silicon, but it needs to be run before trying to send any data packets.

    Regards,

    Travis