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Any ideas for reducing power consumption of C5504 USB?

j-breeze
Mastermind 7560 points

Hi C5000 Champs,

I am looking for the method to reduce the power consumption of C5504 USB when it operate at full speed mode.
Any ideas would be appreciated.

As my idea, can I set USB PHY PLL freq to under 60MHz?

Thanks in advance for your cooperation.

Best regards,
j-breeze

  • 0
    TI__Mastermind 23785 points

    I believe you are referring to the USB subsystem peripheral clcok, which must be at least 30 MHz for proper USB operation. Please refer to USB User's Guide under "Clock Control" section.

    Clock Control

    Figure 13-2 shows the clock connections for the USB2.0 module. Note that there is a built-in oscillator that generates a 12 MHz reference clock for the internal PLL of the USB 2.0 subsystem. The USB2.0 subsystem peripheral bus clock is sourced from the system clock (SYSCLK).

    NOTE: The device system clock (SYSCLK) must be at least 30 MHz for proper USB operation.

    Regards.