hi,
I got an error when I built my server. here is my print information:
"/opt/dvsdk/xdctools_3_16_03_36/xdc" XDCOPTIONS= XDCARGS="CODEGEN_INSTALL_DIR=\"/opt/dvsdk/cgt6x_6_1_14\"" --xdcpath="/opt/dvsdk/xdctools_3_16_03_36/packages\;/opt/dvsdk/codec-engine_2_26_02_11/packages\;/opt/dvsdk/framework-components_2_26_00_01/packages\;/opt/dvsdk/dsplink_1_65_00_02\;/opt/dvsdk/codecs-omap3530_4_02_00_00/packages\;/opt/dvsdk/dspbios_5_41_03_17/packages\;/opt/dvsdk/biosutils_1_02_02/packages\;/opt/dvsdk/edma3lld_01_11_00_03/packages\;/opt/dvsdk/xdais_6_26_01_03/packages\;/opt/dvsdk/linuxutils_2_26_01_02/packages\;/opt/dvsdk/linuxutils_2_26_01_02/packages\;/opt/dvsdk/cgt6x_6_1_14\;/opt/dvsdk/dmai_2_20_00_15/packages\;/opt/dvsdk/local-power-manager_1_24_02_09/packages\;/opt/dvsdk/linux-devkit/arm-none-linux-gnueabi/usr\;/opt/dvsdk/c6accel_1_01_00_06/soc/packages\;/opt/dvsdk/c6run_0_95_02_02\;/opt/dvsdk/omap35x_graphics_sdk_4.00.00.01/packages;/home/wangth/workdir/camera/demos/packages" release
making package.mak (because of package.bld) ...
building for target C64P ...
generating interfaces for package servers.platenet (because package/package.xdc.inc is older than package.xdc) ...
configuring bin/platenet.x64P from package/cfg/bin/platenet_x64P.cfg ...
platform = ti.platforms.evm3530
undefined.createMemMapFile(): progName = bin/platenet_x64P
NOTE: You can find the complete server data sheet in ./package/info/bin/platenet.x64P.DataSheet.html
----------------------------------------------------------------------------------------------------
Warning: incompatible use of package 'ti.sdo.edma3.rm' [in /opt/dvsdk/edma3lld_01_11_00_03/packages/ti/sdo/edma3/rm/]: version of the loaded package 'ti.sdo.edma3.rm' is [01, 03, 07], while 'ti.sdo.fc.dman3' [in /opt/dvsdk/framework-components_2_26_00_01/packages/ti/sdo/fc/dman3/] was built with 'ti.sdo.edma3.rm' [01, 03, 08, 1276531399079], while 'ti.sdo.fc.edma3' [in /opt/dvsdk/framework-components_2_26_00_01/packages/ti/sdo/fc/edma3/] was built with 'ti.sdo.edma3.rm' [01, 03, 08, 1276531399079]
algRecs[PLATENET_CODECS_IPLATENET] = ti.sdo.ce.universal.IUNIVERSAL
Auto register ti.sdo.fc.ires.edma3chan.EDMA3CHAN
will link with codecs.platenet:lib/release/platenet.a64P
will link with ti.sdo.ce.universal:lib/release/universal.a64P
will link with ti.sdo.ce.bioslog:lib/release/bioslog.a64P
will link with ti.sdo.ce:lib/release/ce.a64P
will link with ti.sdo.ce.alg:lib/release/Algorithm_BIOS.a64P
will link with ti.sdo.ce.ipc.bios:lib/release/ipc_bios.a64P
will link with ti.sdo.ce.osal.bios:lib/osal_bios.a64P
will link with ti.sdo.ce.osal.bios:lib/osal_bios_pwrm.a64P
will link with ti.bios.utils:lib/utils.a64P
will link with ti.sdo.fc.acpy3:lib/release/acpy3.a64P
will link with ti.sdo.fc.memutils:lib/release/memutils.a64P
will link with ti.sdo.ce.utils.xdm:lib/release/XdmUtils.a64P
will link with ti.sdo.ce.node:lib/release/node.a64P
will link with ti.sdo.fc.ires.edma3chan:lib/release/edma3Chan.a64P
will link with ti.sdo.fc.dman3:lib/release/dman3RMCfg.a64P
will link with ti.sdo.fc.edma3:lib/release/edma3.a64P
will link with ti.sdo.fc.rman:lib/release/rman.a64P
will link with ti.sdo.fc.dskt2:lib/release/dskt2.a64P
will link with ti.sdo.utils.trace:lib/release/gt.a64P
will link with ti.sdo.fc.ires.nullresource:lib/release/nullres.a64P
Inside EDMA3 RM getLibs
will link with ti.sdo.edma3.rm:lib/omap35xx/Release/edma3_rm_bios.lib
cl64P main.c ...
asm64P package/cfg/bin/platenet_x64Pcfg.s62 ...
cl64P package/cfg/bin/platenet_x64P.c ...
cl64P package/cfg/bin/platenet_x64Pcfg_c.c ...
lnk64P bin/platenet.x64P ...
undefined first referenced
symbol in file
--------- ----------------
_EDMA3_DRV_enableTransfer ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_freeChannel ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_getPaRAM ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_requestChannel ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_setDestParams ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_setOptField ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_setPaRAM ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_EDMA3_DRV_setSrcParams ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
_hEdma ../../lib/TH_PlateNet.lib<TH_PlateNet.obj>
error: unresolved symbols remain
error: errors encountered during linking; "bin/platenet.x64P" not built
gmake: *** [bin/platenet.x64P] Error 1
make: *** [all] Error 2
And here is my .cfg file:
/*
* ======== server.cfg ========
*
* For details about the packages and configuration parameters used throughout
* this config script, see the Codec Engine Configuration Guide (link
* provided in the release notes) and the Codec Engine Package Documentation at:
* http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ce/latest_2_x/xdoc/index.html
* which references to Framework Components configurable modules under ti.sdo.fc.
*/
/* scratch groups */
var MAXGROUPS = 20;
var GROUP_2 = 2;
/*
* Configure CE's OSAL. This codec server only builds for the BIOS-side of
* a heterogeneous system, so use the "DSPLINK_BIOS" configuration.
*/
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;
/*
* Uncomment and modify the following line, to change the size of the circular
* trace buffer, if necessary.
*/
//osalGlobal.traceBufferSize = 32 * 1024;
/* configure default memory seg id to BIOS-defined "DDR2" */
osalGlobal.defaultMemSegId = "DDR2";
/* activate BIOS logging module */
var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');
/*
* ======== Server Configuration ========
*/
var Server = xdc.useModule('ti.sdo.ce.Server');
/* The server's stackSize. More than we need... but safe. */
Server.threadAttrs.stackSize = 16384;
/* The servers execution priority */
Server.threadAttrs.priority = Server.MINPRI;
/*
* The optional stack pad to add to non-configured stacks. This is well
* beyond most codec needs, but follows the approach of "start big and
* safe, then optimize when things are working."
*/
Server.stackSizePad = 9000;
utils.importFile("codec.cfg");
/* to link in debug/trace FC libs, uncomment one of these */
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug");
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug_trace");
// xdc.useModule('ti.sdo.fc.global.Settings').profile = "trace");
/*
* ======== DSKT2 (XDAIS Alg. memory allocation) configuration ========
*
* DSKT2 is the memory manager for all algorithms running in the system,
* granting them persistent and temporary ("scratch") internal and external
* memory. We configure it here to define its memory allocation policy.
*
* DSKT2 settings are critical for algorithm performance.
*
* First we assign various types of algorithm internal memory (DARAM0..2,
* SARAM0..2,IPROG, which are all the same on a C64+ DSP) to "L1DHEAP"
* defined in the .tcf file as an internal memory heap. (For instance, if
* an algorithm asks for 5K of DARAM1 memory, DSKT2 will allocate 5K from
* L1DHEAP, if available, and give it to the algorithm; if the 5K is not
* available in the L1DHEAP, that algorithm's creation will fail.)
*
* The remaining segments we point to the "DDRALGHEAP" external memory segment
* (also defined in the.tcf) except for DSKT2_HEAP which stores DSKT2's
* internal dynamically allocated objects, which must be preserved even if
* no codec instances are running, so we place them in "DDR2" memory segment
* with the rest of system code and static data.
*/
var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
DSKT2.DARAM0 = "L1DHEAP";
DSKT2.DARAM1 = "L1DHEAP";
DSKT2.DARAM2 = "L1DHEAP";
DSKT2.SARAM0 = "L1DHEAP";
DSKT2.SARAM1 = "L1DHEAP";
DSKT2.SARAM2 = "L1DHEAP";
DSKT2.ESDATA = "DDRALGHEAP";
DSKT2.IPROG = "L1DHEAP";
DSKT2.EPROG = "DDRALGHEAP";
DSKT2.DSKT2_HEAP = "DDR2";
/*
* Next we define how to fulfill algorithms' requests for fast ("scratch")
* internal memory allocation; "scratch" is an area an algorithm writes to
* while it processes a frame of data and is discarded afterwards.
*
* First we turn off the switch that allows the DSKT2 algorithm memory manager
* to give to an algorithm external memory for scratch if the system has run
* out of internal memory. In that case, if an algorithm fails to get its
* requested scratch memory, it will fail at creation rather than proceed to
* run at poor performance. (If your algorithms fail to create, you may try
* changing this value to "true" just to get it running and optimize other
* scratch settings later.)
*
* Setting "algorithm scratch sizes", is a scheme we use to minimize internal
* memory resources for algorithms' scratch memory allocation. Algorithms that
* belong to the same "scratch group ID" -- field "groupId" in the algorithm's
* Server.algs entry above, reflecting the priority of the task running the
* algorithm -- don't run at the same time and thus can share the same
* scratch area. When creating the first algorithm in a given "scratch group"
* (between 0 and 19), a shared scratch area for that groupId is created with
* a size equal to SARAM_SCRATCH_SIZES[<alg's groupId>] below -- unless the
* algorithm requests more than that number, in which case the size will be
* what the algorithm asks for. So SARAM_SCRATCH_SIZES[<alg's groupId>] size is
* more of a groupId size guideline -- if the algorithm needs more it will get
* it, but getting these size guidelines right is important for optimal use of
* internal memory. The reason for this is that if an algorithm comes along
* that needs more scratch memory than its groupId scratch area's size, it
* will get that memory allocated separately, without sharing.
*
* This DSKT2.SARAM_SCRATCH_SIZES[<groupId>] does not mean it is a scratch size
* that will be automatically allocated for the group <groupId> at system
* startup, but only that is a preferred minimum scratch size to use for the
* first algorithm that gets created in the <groupId> group, if any.
*
* (An example: if algorithms A and B with the same groupId = 0 require 10K and
* 20K of scratch, and if SARAM_SCRATCH_SIZES[0] is 0, if A gets created first
* DSKT2 allocates a shared scratch area for group 0 of size 10K, as A needs.
* If then B gets to be created, the 20K scratch area it gets will not be
* shared with A's -- or anyone else's; the total internal memory use will be
* 30K. By contrast, if B gets created first, a 20K shared scratch will be
* allocated, and when A comes along, it will get its 10K from the existing
* group 0's 20K area. To eliminate such surprises, we set
* SARAM_SCRATCH_SIZES[0] to 20K and always spend exactly 20K on A and B's
* shared needs -- independent of their creation order. Not only do we save 10K
* of precious internal memory, but we avoid the possibility that B can't be
* created because less than 20K was available in the DSKT2 internal heaps.)
*
* Finally, note that if the codecs correctly implement the
* ti.sdo.ce.ICodec.getDaramScratchSize() and .getSaramScratchSize() methods,
* this scratch size configuration can be autogenerated by
* configuring Server.autoGenScratchSizeArrays = true.
*/
DSKT2.ALLOW_EXTERNAL_SCRATCH = false;
DSKT2.SARAM_SCRATCH_SIZES[GROUP_2] = 0x0000;
DSKT2.DARAM_SCRATCH_SIZES[GROUP_2] = 0x0000;
/*
* ======== DMAN3 (DMA manager) configuration ========
*/
/* First we configure how DMAN3 handles memory allocations:
*
* Essentially the configuration below should work for most codec combinations.
* If it doesn't work for yours -- meaning an algorithm fails to create due
* to insufficient internal memory -- try the alternative (commented out
* line that assigns "DDRALGHEAP" to DMAN3.heapInternal).
*
* What follows is an FYI -- an explanation for what the alternative would do:
*
* When we use an external memory segment (DDRALGHEAP) for DMAN3 internal
* segment, we force algorithms to use external memory for what they think is
* internal memory -- we do this in a memory-constrained environment
* where all internal memory is used by cache and/or algorithm scratch
* memory, pessimistically assuming that if DMAN3 uses any internal memory,
* other components (algorithms) will not get the internal memory they need.
*
* This setting would affect performance very lightly.
*
* By setting DMAN3.heapInternal = <external-heap> DMAN3 *may not* supply
* ACPY3_PROTOCOL IDMA3 channels the protocol required internal memory for
* IDMA3 channel 'env' memory. To deal with this catch-22 situation we
* configure DMAN3 with hook-functions to obtain internal-scratch memory
* from the shared scratch pool for the associated algorithm's
* scratch-group (i.e. it first tries to get the internal scratch memory
* from DSKT2 shared allocation pool, hoping there is enough extra memory
* in the shared pool, if that doesn't work it will try persistent
* allocation from DMAN3.internalHeap).
*/
var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');
DMAN3.useExternalRM = true;
DMAN3.heapInternal = "L1DHEAP"; /* L1DHEAP is an internal segment */
DMAN3.heapExternal = "DDRALGHEAP";
DMAN3.idma3Internal = false;
DMAN3.scratchAllocFxn = "DSKT2_allocScratch";
DMAN3.scratchFreeFxn = "DSKT2_freeScratch";
/*
* ======== RMAN (IRES Resource manager) configuration ========
*/
var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
RMAN.useDSKT2 = true;
RMAN.tableSize = 10;
RMAN.semCreateFxn = "Sem_create";
RMAN.semDeleteFxn = "Sem_delete";
RMAN.semPendFxn = "Sem_pend";
RMAN.semPostFxn = "Sem_post";
/* The lock/unlock/set/getContext functions will default to DSKT2 */
var EDMA3 = xdc.useModule('ti.sdo.fc.edma3.Settings');
EDMA3.globalInit = true;
EDMA3.maxTccs[GROUP_2] = 0;
EDMA3.maxPaRams[GROUP_2] = 0;
EDMA3.maxQdmaChannels[GROUP_2] = 0;
var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');
How can I fix it?
Thanks.
Tianhe Wang
