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AM335x LCD controller register?

DavidVescovi
Genius 5470 points

My Windows CE BSP seems to be using a LCD register that does not appear in the documentation (TRM G).

The register is at offset 0x68h and in the code it is defined as "IRQEoi_vector". I do not know if this code is really needed and the documentation is wrong or if the documentation is right and its just dead code ...probably ported from an earlier BSP or sister silicon BSP??

The display controller seems to be working so I guess it is harmless but I would like to know.

They also define a "status" register at offset 0x08h

Are these two resisters really present and/or used on the AM335x?

 

  • 0
    TI__Intellectual 1980 points

    David, 

    The register at 0x68 is the end of interrupt register. It's no longer necessary to use this register and any references to it are from older code. As for the register at 0x08, that one no longer exists.

    -Tyler

  • 0 in reply to Tyler Berryhill
    Genius 5470 points

    If the EOI register is no longer available (it is still referenced several places in the TRM) then what is the proper way to clear pending interrupts in the ISR?

    The TRM does not seem to be consistent. For sync lost and FUF I guess you have to disable and then renable the raster en bit?

    Does disable/enable clear all irq status bits? I am use to clearing other interrupts (other peripherals) by writing to the IRQSTATUS register with the bit that is set indicating the interrupt source but for this LCD controller writes to the IRQSTATUS register have no effect ..at least accourding to the TRM.

    confused.

  • 0 in reply to DavidVescovi
    Genius 5470 points

    I think I figured it out. You write to the IRQSTATUS to clear the interrupt pending status. I guess i was confused by the naming of the bit fileds in the IRQSTATUS register.

    They seem to overload the term "enable" when these bit have nothing to do with enabling ... they are interrupt pending status bits.

  • 0 in reply to DavidVescovi
    TI__Intellectual 1980 points

    David,

    You're right. I was in the process of replying to your post but I'm glad you noticed the behavior. I think the descriptions are a mistake in the TRM. It looks like the description of the IRQENABLE_CLR and IRQSTATUS are exactly the same.

    -Tyler