Hello,
I have a custom board with AM3352 and DDR3-memory. I want to use the Suspend mode, but when I let the processor longer in Suspend than about 10 seconds, Kernel crashes at wakeup. If I wake it up faster than 10 seconds, it works.
I suppose a problem with DDR-Self-Refresh.
Can you give me some Ideas, where I can search?
Thanks, Philipp
Hi,
i have an issue about wakeup form suspend to ram with DDR3 400MHz in my custon board based on AM335x Starter Kit.
After VTT_EN goes high, NO CKE goes high but the differential clock is present and stable.
See image
LOG:
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|
Arago Project http://arago-project.org am335x-evm ttyO0
Arago 2012.10 am335x-evm ttyO0
am335x-evm login: root
root@am335x-evm:~# echo mem > /sys/power/state
[ 87.983306] PM: Syncing filesystems ... done.
[ 88.003692] Freezing user space processes ... (elapsed 0.01 seconds) done.
[ 88.026733] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
[ 88.062469] PM: suspend of devices complete after 15.014 msecs
[ 88.073699] PM: late suspend of devices complete after 4.974 msecs
....
No other output
The same board is working with 303MHz DDR3 configuration.
A big differece: the time between VTT_EN and CLOCK
400MHz is every time 1.6us
303MHZ is variable 10us-200us
Any ideas ?
I made a suspend-to-ram on AM335x Starter Kit with
Linux http://arago-project.org/git/projects/linux-am33x.git?p=projects/linux-am33x.git;a=shortlog;h=refs/heads/v3.2-staging
Uboot http://arago-project.org/git/projects/u-boot-am33x.git?p=projects/u-boot-am33x.git;a=shortlog;h=refs/heads/master
but suspend-to-ram with DDR3 400MHz dosen't works: CKE is LOW
_____ _____ _ _
| _ |___ ___ ___ ___ | _ |___ ___ |_|___ ___| |_
| | _| .'| . | . | | __| _| . | | | -_| _| _|
|__|__|_| |__,|_ |___| |__| |_| |___|_| |___|___|_|
|___| |___|
Arago Project http://arago-project.org am335x-evm ttyO0
Arago 2011.09 am335x-evm ttyO0
am335x-evm login: root
root@am335x-evm:~# echo mem > /sys/power/state
[ 41.045837] PM: Syncing filesystems ... done.
[ 42.664459] Freezing user space processes ... (elapsed 0.01 seconds) done.
[ 42.688903] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
[ 42.708923] Suspending console(s) (use no_console_suspend to debug)
Standby works... The DDR3 wakeup corretly
root@am335x-evm:~# echo standby > /sys/power/state [ 50.286987] PM: Syncing filesystems ... done. [ 51.809783] Freezing user space processes ... (elapsed 0.01 seconds) done. [ 51.834014] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. [ 51.854003] Suspending console(s) (use no_console_suspend to debug) [ 51.882202] PM: suspend of devices complete after 20.843 msecs [ 51.887390] PM: late suspend of devices complete after 5.096 msecs [ 53.408233] GFX domain entered low power state [ 53.408355] Successfully transitioned all domains to low power state [ 53.411285] PM: early resume of devices complete after 2.532 msecs [ 53.628479] net eth0: CPSW phy found : id is : 0x4dd074 [ 53.630676] PM: resume of devices complete after 218.644 msecs [ 53.673553] Restarting tasks ... done. standby root@am335x-evm:~#
The differemce is the time between VTT_EN and CLOCK.
Uboot patch for 400MHz
---------------------- arch/arm/cpu/armv7/am33xx/emif4.c ----------------------
index 2d2014e..689171b 100644
@@ -166,7 +166,8 @@ void config_ddr(short ddr_type)
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
- ddr_pll = 303;
+ //ddr_pll = 303;
+ ddr_pll = 400;
ioctrl_val = DDR3_IOCTRL_VALUE;
cmd_ctrl_data = &ddr3_cmd_ctrl_data;
if (board_is_evm_15_or_later()) {
----------------- arch/arm/include/asm/arch-am33xx/ddr_defs.h -----------------
index 7aac2c9..4e80337 100644
@@ -48,12 +48,17 @@
#define DDR2_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY 0x100006 /* Enable Dynamic Power Down */
-#define DDR3_EMIF_TIM1 0x0888A39B
-#define DDR3_EMIF_TIM2 0x26337FDA
-#define DDR3_EMIF_TIM3 0x501F830F
+//#define DDR3_EMIF_READ_LATENCY 0x100006 /* Enable Dynamic Power Down */
+#define DDR3_EMIF_READ_LATENCY 0x07
+//#define DDR3_EMIF_TIM1 0x0888A39B
+#define DDR3_EMIF_TIM1 0x0AAAE4DB
+//#define DDR3_EMIF_TIM2 0x26337FDA
+#define DDR3_EMIF_TIM2 0x26437FDA
+//#define DDR3_EMIF_TIM3 0x501F830F
+#define DDR3_EMIF_TIM3 0x501F83FF
#define DDR3_EMIF_SDCFG 0x61C04AB2
-#define DDR3_EMIF_SDREF 0x0000093B
+//#define DDR3_EMIF_SDREF 0x0000093B
+#define DDR3_EMIF_SDREF 0x00000C30
#define DDR3_ZQ_CFG 0x50074BE4
#define DDR3_DLL_LOCK_DIFF 0x1
#define DDR3_RATIO 0x40
@@ -65,8 +70,10 @@
#define DDR3_IOCTRL_VALUE 0x18B
/* Micron ???? on 1.5 and later EVMs */
-#define DDR3_EMIF_TIM2_EVM 0x26517FDA
-#define DDR3_EMIF_TIM3_EVM 0x501F851F
+//#define DDR3_EMIF_TIM2_EVM 0x26517FDA
+#define DDR3_EMIF_TIM2_EVM 0x26437FDA
+//#define DDR3_EMIF_TIM3_EVM 0x501F851F
+#define DDR3_EMIF_TIM3_EVM 0x501F83FF
#define DDR3_RD_DQS_EVM 0x3A
#define DDR3_WR_DQS_EVM 0x0CD
#define DDR3_PHY_FIFO_WE_EVM 0x10B
Thanks
Paolo