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AM335x Pin Mux conflcit resolution between LCD [16:23] and GPMC-AD[8:15]

K Md Feroz Irfan
Expert 7225 points

Dear Sitara Champs,

We are looking for a solution for the issue that customer is facing with the multiplexing of the GPMC_AD lines.

 

  1. GPMC_AD8 to GPMC_AD15 are sharing with
    1. External Memory interface data bus
    2. LCD interface (Lower Byte LCD_Data16 to LCD_Data23)
  2. GPMC_AD0 to GPMC_AD7 are sharing with
    1. External Memory interface data bus

b.      NAND Flash interface

Can you please help us on this?

 

My comments:

 

On the conflict between 2a and 2b i.e.  Ext memory interface and Nand, if Nand will only be used during boot…it’s a non-issue perhaps since there is DDR3 for boot. Please comment here …

 

The challenge is 1a and 1b conflict where GPMC will be connected to ext memory and LCD’s HSB. LCD has to be 24 bit and they need to operate simultaneously …Is there a way we can do some latching or buffering to ensure simultaneous operation. Has this been done before by any of our customers ?

 

Kindly let us know…

 

Thanks.

Best Regards

Feroz

  • 0
    TI__Expert 6735 points

    Please post the File > Save > Design data file from Pin Mux Utility.

    http://www.ti.com/tool/pinmuxtool

    MichaelT

  • 0 in reply to Michael T
    TI__Expert 7225 points

    Hi Michael,

    Thanks for looking into this.

    Here you go...2018.AM3357 PIN ASSIGNMENT.dat

    I hope the issue is clear enough. It is about the 2 conflicts above. And how we can build a board circumventing  these. 

    Any thoughts also on alternate interfaces OR latches/buffers would be very useful....

    Best Regards

    Feroz

  • 0 in reply to K Md Feroz Irfan
    TI__Expert 6735 points

    I don't see a reason why this would not work.

     The LCD would have to be disabled while the NAND is active otherwise there may be garbage on the screen.

     Once the LCD is enabled and pinmux adjusted, the NAND would have to be configured or disabled so that the LCD operation is uneffected. 

    I'm not aware of any examples for this configuration.

    Care should be taken when routing the signals to avoid stubs. Also, the timing of the nand interface timing should be checked to ensure that the loading of the LCD has no negative impact on the NAND timing.

    MichaelT (from ARM MPU HW Apps Team)

  • 0 in reply to Michael T
    TI__Expert 6735 points

    With the LCD there is a LIDD mode which updates the LCD only when a change is to be made and there is a RASTER mode

    which continuously updates the LCD.  The RASTER mode would be out of the question if NAND and LCD need to share the same

    ball locations.  But LIDD mode LCD + NAND may be possible.  If you just need NAND at bootup, and there is no rootfs in NAND,

    that is an easier case to deal with.

    MichaelT (from peaves)

  • 0 in reply to Michael T
    TI__Expert 7225 points

    Hi Michael,

    Thanks for the inputs.  I am sure these will help us convince customer to tone done the specs.

    Have you considered the possibility that the 3rd device can be CPLD along with LCD and NAnd? How does it look?

    Have you/anyone used a latch/buffer in such a scenario? Any advice on that front if the LCD has to be 24 bit Raster and CPLD is also used simulateously?

    Thanks again!

    Best Regards

    Feroz

  • 0 in reply to K Md Feroz Irfan
    TI__Expert 7225 points

    Hi Micheal,

    The schematic reference that I have considered for latching is:

    Design File Name: AM335X_15X15_ICE.dsn (Page no.8)

     

    In which GPMC_AD0 - GPMC_AD15 are multiplexed and GPMC_A0 - GPMC_A0 are derived from the latch (SN74ALVCH16374DGV ).

    And using between Dual-Port Static RAM (CY7C024AV/025AV/026AV) & NOR Flash (M29W160EB70ZA6E).

     

    Could this somehow be used? Sorry I am yet to study this option in detail. Any quick inputs would be of great help..

    Thanks & Regards,

    Feroz