memory usage

1330hayacool7102

Hi TI friends,

As we know, we can limit the memory capacity in kernel from bootargs in uboot. I have following question

Q1. But how did we know the memory capacity for each of M3 Video/M3 VPSS/DSP?

Q2. how did we know the consuming memory and residual memory in each of M3 Video/M3 VPSS/DSP? just like "top" command in A8 side.

over 13 years ago

0 Badri Narayanan over 13 years ago

TI__Guru 59700 points

On 816x 3 memory configurations are supported.

1G total DDR memory with 128M for Linux :/dvr_rdk/mcfw/src_bios6/cfg/ti816x/config_1G_128MLinux.bld

1G total DDR memory with 256M for Linux:/dvr_rdk/mcfw/src_bios6/cfg/ti816x/config_1G_256MLinux.bld

2G total DDR memory :/dvr_rdk/mcfw/src_bios6/cfg/ti816x/config_2G.bld

The corresponding bld file has memory size allocated for each segment.

To know the size consumed for Program and Data section refer the generated map file for each core M3Video/M3Vpss/c674x under

/dvr_rdk/build/dvr_rdk/bin/ti816x-evm

To know the size consumed from the shared region heaps invoke the Vsys_printDetailedStatistics() API which will print total size and free size

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

Hi badri,

thanks for your reply.

by chekcing, we use config_1G_256MKinux.bld. And I have question

Q1. By following description inside config_1G_256MKinux.bld, how does TI decide each value for the corresponding item?

/* first 512MB */
LINUX_SIZE                 = 256*MB;
SR1_SIZE                   = 208*MB;
SR3_INTRADUCATI_IPC_SIZE   = 124*KB;
VIDEO_M3_CODE_SIZE         = 2.5*MB;
VIDEO_M3_BSS_SIZE          = 11.5*MB;
VIDEO_M3_DATA_SIZE         = 0.5*MB;
DSS_M3_CODE_SIZE           = 1.5*MB;
DSS_M3_BSS_SIZE            = 15.5*MB;
DSS_M3_DATA_SIZE           = 1.8*MB;
DSP_CODE_SIZE              = 900*KB;
DSP_DATA_SIZE              = 13.7*MB;

/* second 512MB */
/* Tiler Buffers in the bottom 512MB */
TILER_SIZE                 = 128*MB; /* (128+128) - MUST be aligned on 128MB boundary */
SR2_FRAME_BUFFER_SIZE      = 362*MB - 256*KB;
SR0_SIZE                   = 15*MB;
VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;
VPSS_M3_EXCEPTION_CTX_SIZE = 128*KB;
HDVPSS_DESC_SIZE           = 2*MB;
HDVPSS_SHARED_SIZE         = 2*MB;
NOTIFY_SHARED_SIZE         = 2*MB;
REMOTE_DEBUG_SIZE          = 1*MB;

0 Sivagamy Govindasamy over 13 years ago in reply to 1330hayacool7102

TI__Expert 6950 points

Memory configuration is decided based on available physical memory, required linux memory, use case memory requirements.

Sections like Code, data mostly remain constant irrespective of use case due to fixed code / data structures for the framework.

Shared Region sections - SR0, SR1, SR2 etc are determined based on memory analysis for various buffer requirements of links. You compare the various memory configurations to get more details.

Few use cases might not be possible if there is stringent requirement of memory.

Analysing memory map, runtime memory statistics will help to understand better.

0 1330hayacool7102 over 13 years ago in reply to Sivagamy Govindasamy

Guru 10655 points

Shared Region sections - SR0, SR1, SR2 etc are determined based on memory analysis for various buffer requirements of links.

- By your speaking, it's better to re-arrange the Shared region for different application. Right?

Is it possible to change the range of shared region dynamically? If yes, how ?

0 Sivagamy Govindasamy over 13 years ago in reply to 1330hayacool7102

TI__Expert 6950 points

1. You could re-arrange shared region, but you need to take care of the caching requirement of some shared regions - eg SR1 (which is used for bitstream buffers). Also, you need to ensure that the device specific alignment / address requirements for few sections - like tiler section for eg.

2. Dynamic range of shared region after starting DVR RDK application is not supported.

0 1330hayacool7102 over 13 years ago in reply to Sivagamy Govindasamy

Guru 10655 points

in rdk, there're several shared regions(SR0/1/2/...), basically they're part of DDR dram. right?

if yes, all they have "caching" characteristic. right? if yes, why not all shared regions are "cacheable"?

and how did you decide which parts should be cacheable, which parts shouldn't be?

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

hi badri,

let me double confirm

Badri Narayanan said:

To know the size consumed for Program and Data section refer the generated map file for each core M3Video/M3Vpss/c674x under /dvr_rdk/build/dvr_rdk/bin/ti816x-evm

did you mean the following?

Badri Narayanan said:

To know the size consumed from the shared region heaps invoke the Vsys_printDetailedStatistics() API which will print total size and free size

did you mean the following?

[m3vpss ] 60348885: SYSTEM : FREE SPACE : System Heap      = 5704 B, Mbx = 10236 msgs)
[m3vpss ] 60348885: SYSTEM : FREE SPACE : SR0 Heap         = 11003648 B (10 MB)
[m3vpss ] 60348885: SYSTEM : FREE SPACE : Frame Buffer     = 980045952 B (934 MB)
[m3vpss ] 60348885: SYSTEM : FREE SPACE : Bitstream Buffer = 218627968 B (208 MB)
[m3vpss ] 60348886: SYSTEM : FREE SPACE : Tiler Buffer     = 127 B (0 MB) - TILER OFF

let's map as below, are they correct ???

[m3vpss ] 60348885: SYSTEM : FREE SPACE : System Heap      = 5704 B, Mbx = 10236 msgs)     --> ???
[m3vpss ] 60348885: SYSTEM : FREE SPACE : SR0 Heap         = 11003648 B (10 MB)                    --> SR0_SIZE
[m3vpss ] 60348885: SYSTEM : FREE SPACE : Frame Buffer     = 980045952 B (934 MB)               -->  SR2_FRAME_BUFFER_SIZE
[m3vpss ] 60348885: SYSTEM : FREE SPACE : Bitstream Buffer = 218627968 B (208 MB)              --> SR1_SIZE
[m3vpss ] 60348886: SYSTEM : FREE SPACE : Tiler Buffer     = 127 B (0 MB) - TILER OFF            --> TILER_SIZE

0 1330hayacool7102 over 13 years ago in reply to 1330hayacool7102

Guru 10655 points

hi badri,

could you help to clarify if the above mapping is correct? Thanks.

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

Above is allocated size.To know the used size look the map file under /dvr_rdk/build/dvr_rdk/bin/ti816x-evm

Above mapping is correct. System heap is core private heap. It is configured in

/dvr_rdk/mcfw/src_bios6/cfg/ti816x/BIOS_m3vpss.cfg

/dvr_rdk/mcfw/src_bios6/cfg/ti816x/BIOS_m3video.cfg

Memory.defaultHeapSize = 0x15000;

/dvr_rdk/mcfw/src_bios6/cfg/ti816x/FC_RMAN_IRES_c6xdsp.cfg

heapMemParams.size              = heapMemParams.size;
heapMemParams.sectionName       = ".systemHeap";
var heap0                       = HeapMem.create(heapMemParams);
Memory.defaultHeapInstance      = heap0;

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

hi badri,

thanks for your reply. I have more question

Q1. about the following, does it mean the minimum memory requirement for tiler is 128MB?

if we don't use tiler, could I set it to zero? if not, why?

TILER_SIZE = 128*MB; /* (128+128) - MUST be aligned on 128MB boundary */

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

If you don't use TILER memory , the memory is automatically used as normal memory.Just invoke System_tilerDisableAllocator at the start of usecase. Refer multich_vdec_vdis.c for example. There is no need to change memory map.

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

If you don't use TILER memory , the memory is automatically used as normal memory.

- what does "normal buffer" mean ?? SR0? VIDEO_M3_EXCEPTION_CTX?

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

SR2_FRAME_BUFFER

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

Badri Narayanan said:

Above is allocated size.To know the used size look the map file under /dvr_rdk/build/dvr_rdk/bin/ti816x-evm

hi badri,

After checking dvr_rdk_c6xdsp_debug.xe674.map under this folder I found following, and I check table 2-26 in document sprs614b.pdf

Q1. why the DSP_L2_RAM is different ?? and others are the same

dvr_rdk_c6xdsp_debug.xe674.map

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
---------------------- -------- --------- -------- -------- ---- --------
DSP_L2_RAM            10800000   00020000 00020000 00000000 RWIX
OCMC0_RAM             40300000   00040000 00000000 00040000 RWIX
OCMC1_RAM             40400000   00040000 00000000 00040000 RWIX

sprs614b.pdf

Table 2-26. L3 Memory Map
QUAD BLOCK NAME START ADDRESS END ADDRESS SIZE DESCRIPTION (HEX) (HEX)
Q1 L3 OCMC0 0x4030 0000 0x4033 FFFF 256KB OCMC SRAM
Q1 L3 OCMC1 0x4040 0000 0x4043 FFFF 256KB OCMC SRAM
Q1 C674x 0x4080 0000 0x4083 FFFF 256KB C674x UMAP0 (L2 RAM)

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

DSP L2 SRAM should be the GEM address view and not the L3 address view. So it is mapped to 10800000.Refer data sheet for c674 view of memory address for details

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

hi badri,

by checking sprs614d.pdf, I found following and the mapping address is 0x0080-0000 instead of 0x1080-0000.

Is there something I miss??

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

See comment at end of the table which explains. Global internal address should be used

(1) Addresses 0x0000 0000 to 0x017F FFFF are internal to the C674x device.
(2) Addresses 0x0180 0000 to 0x01BF FFFF are reserved for C674x internal CFG registers.
(3) Addresses 0x01C0 0000 to 0x0FFF FFFF are mapped to the C674x CFG bus.
(4) Addresses 0x1000 0000 to 0x10FF FFFF are mapped to C674x internal addresses 0x0000 0000 to 0x00FF FFFF.

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

thanks for your reply. I have more question

Q1. what's the difference between "internal address" and "internal global address"?

Q2. why does TI use "internal global address"?

0 Badri Narayanan over 13 years ago in reply to 1330hayacool7102

TI__Guru 59700 points

Q1. what's the difference between "internal address" and "internal global address"?

-- Internal address is the address as seen by c674 processor and IDMA.Internal Global is the address as seen by other initiators like EDMA.

Q2. why does TI use "internal global address"?

-- We should always use global addresses to enable things like EDMA from/to L2 SRAM.

Pls refer below post where this is explained in details.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/7450/29333.aspx#29333

0 1330hayacool7102 over 13 years ago in reply to Badri Narayanan

Guru 10655 points

hi, badri

thanks for your reply. I have more question

Q1. as your explain

DSP_L2_SRAM

0x0080-0000 --> used by DSP

0x1080-0000 --> used by other initiator like EDMA, A8, ...

0x4080-0000 --> used by who ???

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memory usage