This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EMIFA Asynchronous Interface Output delay time

http://www.ti.com/lit/ug/sprufv0a/sprufv0a.pdf
Table 56. AC Characteristics for a Read Access (Page 79)

tD (Output delay time) is defined for the Asynchronous Interface.
 
Is this delay time applied in other cases for the Asynchronous Interface?

Best regards,

Daisuke

 

  • I think that this delay time (tD) is applied in only this case.

    For async interface, can the delay time between the clock (EMA_CLK) and other output signal be specified?

    Best regards,

    Daisuke

     

  • For async interface, must not the clock (EMA_CLK) be used?

    Best regards,

    Daisuke

     

  • Daisuke-san

    When configuring the EMIFA for asynchronous interface, you must consider the AC timing requirements of the Flash as well as the AC timing requirements of the EMIFA. These can be found in the data sheet for each respective device. For the example in Table 56, the AC timing applies to LHF80J01 and EMIFA. Other FLASH devices may have different AC timing spec and therefore result in different calculation value.

    EMA_CLK is not needed for connecting to the FLASH.

    Thanks

    David

  • Hi David-san,

    Thank you for your reply.

    I just understand that the AC timing in Table 56 only applies to LHF80J01 and EMIFA.

    My customer needs the output delay time (EMA_CLK high to output signal valid) for connecting to the FPGA with the async interface.
    I explained it in reference to the datasheet to them that the output delay time is not specified for the async interface.
    Then they checked Table 56 and thought that output delay time might be specified for any async interface.

    I am going to explain it to them that the output delay time is not specified for other connection of the async interface.

    Best regards,

    Daisuke