DM3730 ARM Cache configuration

Hi Pay,

The work with the L2 cache of the ARM core is little bit different then the DSP cache. There is a register - Cache Type Register which determines the instruction and data cache minimum line length in bytes to enable a range of addresses to be invalidated. The Cache Type Register is read-only and accessible in privileged modes only. More details about the Cache Type Register you can find in the Cortex-A8 TRM at the link below:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344f/DDI0344F_cortex_a8_r2p3_trm.pdf

BR

Tsvetolin Shulev

Hi,

thanks for the fast answer, so is it right that I can't use the Cache manually like linking data sections to be placed in it? What I have to do is a comparison of image processing on ARM and DSP and I've learned that the memorymanagement is here one of the basics. On DSP side I placed some buffers in the cache and worked directly on them, I wanted to copy this test to the ARM.

best regards,

Pay Gießelmann

Thank you very much, that was the hint I needed!