I was going through the RBL code (http://software-dl.ti.com/sdoemb/sdoemb_public_sw/rbl/1_0_C6678/index_FDS.html), and noticed that the boot parameter table has a field that is not defined in http://www.ti.com/lit/ug/sprugy5b/sprugy5b.pdf table 3-12. Specifically, PCIe boot parameter table byte offset 12 (Config) is used by the code, but not defined in the document. In the code, config bit 0 is used for host boot vs boot table, bit 1 is used for init vs no init, and bit 4 is used for compute PLL vs no compute PLL. In the document, this field is not defined.
The document does not define where the fields in tables 3-13 and 3-14 come from. Are these defined in hardware using chip external pin settings? If so, which external pins?
In section 3.4.1, the document says, “PCIe boot code can configure the PCIe registers either by getting the values from the I2C or the default values from the boot parameter table”. There are no further details.
If the boot code gets the PCIe register values from I2C, is it getting it from an I2C EEPROM? If so, what is the EEPROM I2C address? At what EEPROM address does the data start? What is the format of the data, i.e. what is the data structure?
If the boot code gets the register values from the boot parameter table, from where is the boot parameter table read?
How does the boot code know whether to get the PCIe register values from I2C or from the boot parameter table? Also, in section 3.4.1, the document says, “If the PCIe boot is the primary boot”. How does one make PCIe the primary boot? If PCIe is not the primary boot, where does the BAR size configuration come from?
The document is incomplete, and causing much frustration. All I want to do is power up the Shannon in PCIe root complex boot mode, and download the image generated by the MAD utility to Shannon. The document gives me no idea how to do this.
