Hello,
I've configured my McBSP as a serial master to read/write data from a USB host controller. It works most of the time, but occasioncally I have an issue where the transmit clock stops working alltogether. If I try to send data, the transmit clock does not change at all and it is as if the clock logic is broken. I know that internally, the McBSP is still running it's clock generator, because when I turn of clock-stop mode, I can see the correct clock waveform being outputted.
Any idea as to what the issue is?
Here is my initialization code:
void mcbsp_init() {
// Initialize for transfer with MAX3421E
gpio_set(GPIO_3, GPIO_LOW); // Put MAX3421 in reset
// First set up channel 0
SPCR1_0 = 0x1800; // Make sure McBSP receiver is in reset
// Right justify, fill zeros, MSB first
// Clock stop mode with half-cycle delay
// Send RINT when RRDY toggled to 1
SPCR2_0 = 0x0200; // Free run (emulation does not affect McBSP)
// Send XINT when XRDY toggles to 1
// Make sure McBSP transmitter is in reset
RCR1_0 = 0x0040; // 1 frame per receive (1 word)
// 16 bits per word
RCR2_0 = 0x0001; // Single phase frame
// 1-bit data delay after sync
XCR1_0 = 0x0040; // 1 frame per transmit (1 word)
// 16 bits per word
XCR2_0 = 0x0001; // Single phase frame
// 1-bit data delay after sync
SRGR1_0 = 0x00FE; // Divide input clock by 255 to generate CLKG
SRGR2_0 = 0x2000; // Take clock from either internal input clock or CLKX
PCR_0 = 0x0a0d; // Set as master in SPI protocol. Sample rate generator drives internal transmit/receive clock.
wait_cycles(0x28); // Repeat NOP for a bunch of cycles to wait till McBSP configured
SPCR1_0 = 0x1801; // Enable receiver
SPCR2_0 = 0x02C1; // Enable transmitter
// Enable frame sync logic
// Enable sample rate generator
// Next, set up channel 1
SPCR1_1 = 0x1800; // Make sure McBSP receiver is in reset
// Right justify, fill zeros, MSB first
// Clock stop mode with half-cycle delay
// Send RINT when RRDY toggled to 1
SPCR2_1 = 0x0200; // Free run (emulation does not affect McBSP)
// Send XINT when XRDY toggles to 1
// Make sure McBSP transmitter is in reset
RCR1_1 = 0x0040; // 1 frame per receive (1 word)
// 16 bits per word
RCR2_1 = 0x0001; // Single phase frame
// 1-bit data delay after sync
XCR1_1 = 0x0040; // 1 frame per transmit (1 word)
// 16 bits per word
XCR2_1 = 0x0001; // Single phase frame
// 1-bit data delay after sync
SRGR1_1 = 0x00FE; // Divide input clock by 255 to generate CLKG
SRGR2_1 = 0x2000; // Take clock from either internal input clock or CLKX
PCR_1 = 0x0a0d; // Set as master in SPI protocol. Sample rate generator drives internal transmit/receive clock.
wait_cycles(0x28); // Repeat NOP for a bunch of cycles to wait till McBSP configured
SPCR1_1 = 0x1801; // Enable receiver
SPCR2_1 = 0x02C1; // Enable transmitter
// Enable frame sync logic
// Enable sample rate generator
// Setup is almost done
gpio_set(GPIO_3, GPIO_HIGH); // Take MAX3421 out of reset
wait_cycles(0xF); // Repeat NOP for a bunch of cycles to wait till McBSP configured
// Blind write some data to make sure that receiver has correct bits set
mcbsp_blind_write_word(0, 0);
}
