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About 6671 MSM

Zhendong Bai
Prodigy 80 points
Other Parts Discussed in Thread: TMS320C6671

I'm developing an application use C6671. As we know, apart form L1 L2 RAM, the 6671 has extra 4M-Byte MSM(multicore shared memory). 
According to the Data sheet(SPRS756C), MSM can be configured as shared L2 and/or shared L3 memory.

My question is:

1.If i want to use MSM as another L2, how to do? I did not find the methord or related register to config.

   And when the MSM is working as the system L2, how about the accessing speed? like local L2?

   What about the accessing speed, when MSM is working as L3?

2.By default( dont change anything), what is MSM's working status ?

3.Which one is more efficient, if I config the MSM as L2 or L3?

looking forward the answer, thanks!

  • 0
    TI__Mastermind 30825 points

    1.) By default it is Shared L2.  The performance of it's access can be found in the Throughput Performance Guide in the Application Notes section of the Product Page -> TMS320C6671.  Details on configuring the MSMC can be found the Mulitcore Shared Memory Controller (MSMC) for Keystone Devices User Guide, it's located in the User Guide section of the product page.

    2.) By default MSMC is Shared L2.

    3.) It depends on if you feel caching this into the Local L2 would be beneficial, and keeping Local L2 more SRAM and using MSMC as another shared L2 and then only caching it into the L1P/L1D spaces.  You'll end up doing more eviction of the local L2 space if you have MSMC as an L3, but it may be worth it to save a few cycles to cache from Local L2 cache than from Share L2 SRAM directly. 

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    Prodigy 80 points

    Thanks for your reply. I will check the Datasheet you provided.

    Could you tell me what is the difference between CorePac L2 and Local L2 on the 6671?

    In my oppinion, there is the only one core on 6671 ,but why they have different physical address (for Corepac L2 and Local L2 )?

    Thank you again.

  • 0 in reply to Zhendong Bai
    TI__Mastermind 30825 points

    They are the same physically.  It's the Global vs Local Addressing.  Keep in mind that the C6671 is built on a multi-core architecture.  The C6678/74/72 and 71 are the exact same architecture but with 8 cores, 4 cores, 2 cores or 1 core. 

    Please note that items outside of the CorePac will need to use the Global (CorePac0 Global) address for accessing this L2 space.  The EDMA doesn't know what the local addresses are for each of the cores in this architecture (yes, C6671 is only one core, but it is a cutdown of the multi-core architecture - There's advantages of this such as scalability of code - It can be designed to run on C6678, but can also run on C6671 w/ no changes if done correctly.)

    Best Regards,
    Chad

  • 0 in reply to Chad Courtney
    Prodigy 80 points

    Thanks Chad, I do exactly understand what you said. And I indeed meet the problem which happened when i use EDMA to transfer data from DDR to L2.  When I use the L2' s local address, the result of transfer is wrong. So for  transfering data to L2 using EDMA, I need to use L2's physical address.

    anyway, thanks a lot.