I am currently working om an EMAC ethernet interface on the EMAC of the TMS320C6657 DSP.
It is to some extend working (e.g. ping) as long as I am using channel 0 only.
When I try to use one of the other channels (e.g. 2 or 4 on CP0), the EMAC completes both transmit
and receive (for an ARP request and reply) and reports the completion in the C0_TX_STAT and C0_RX_STAT
registers at 0x02c0 8a90 and on, but the interrupts don’t get thru to the interrupt controller resp. the CIC0.
The associated events bit are neither set in the interrupt controller event flag register at 0x0180 0000 or,
for the channel 4, in the CIC0 SISR register at 0x0260 0020 and on.
As I need to use more EMAC channels for our application, I would very much appreciate to have ti problem solved.
Niels Svenningsen
Brüel & Kjær Sound & Vibration A/S