EDMA channels priority on OMAP-L138

Hi Boris,

We may need more details of your EDMA configuration  to be able to help you. Are you utilizing both the EDMA queues?Can you provide details of which Events are being assigned to TCC0 and TCC. It is recommended to assign higher priority events to Queue0 as Queue0 will always win arbitration over Queue1. you will always want this to win priority if the two events are submitted by the transfer controller at the same time.That would also mean the higher priority events go to TCC0 instead of TCC1 so you will need to change the priorities of the TCCs as well.

Please refer to this article to gain more insight into the System interconnect to identify bottle necks. The SCR and burst size sections should help you tune your system.

http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SoC_Architectural_Overview

Regards,

Rahul

Hi Rahul.

Thank you for your support.

I was able eventually to make all four serial ports be served by EDMA as required and without any missed events.

To make EDMA work as required - I setup all four events to be as short as possible - that facilitates the fair events arbitration - I think (Is it correct assumption?):

1.  SPI0 events requires to be served every ~450nS because SPI0 runs at ~36MHz and has no FIFO. SPI0 EDMA transfer is configured as A-synchronized for 4Byte.

2.  McASP EDMA transfer is configured as A-synchronized with A-count=8Byte - the minimum possible data size for two McASP port channels. The FIFO is configured for 8Byte only. McASP port was previously configured for the deeper FIFO of 40Bytes (AB-synchronized) and the system of four serial ports did not work properly. I think - it was because McASP event was too long (40Bytes) to serve by EDMA which caused the shorter events (SPI0) to be missed. Is it correct?

3.  McBSP[0:1] transfers are configured as A-synchronized with A-count=4Byte - the minimum possible data size for McBSP receive channel. The FIFO is configured for 4Byte only. It was previously configured also for 40Byte deep AB-synchronized.

4.  After these EDMA re-configuration - all four possible EDMA events have the similar data sizes (SPI0-4Byte every 450nS, McASP-8Byte every 2uS, McBSP0-4Byte every 256uS, McBSP1-4Byte every 256uS)

5.  I also configured SPI0 events to be on Queue0 and other events to be on Queue1 with TC0 priority set=0 and TC1 priority set=1. So TC0 has higher priority than TC1. But this seems to me does not have any significant impact on the system.

6.  All four ports are served by EDMA correctly even with the default settings for Queue0, Queue1 and TC0-TC1 priority.

7.  Just making all required EDMA events short (as described above) allows EDMA to serve all of them as expected. Is it correct statement?

8.  Is there a better way to solve this problem - serve four serial ports with EDMA simultaneously?

8.  Are there any timing parameters available for EDMA transfer?

9.  How long it takes for EDMA to make one single 16Byte burst read? These timing data can be helpful for the system designer to optimize the EDMA configuration.

Thank you very much for your help,

Boris

Hi Boris,

Thanks for the detailed explanation on the solution that worked for you. You are right in your assessment that reducing the event duration lets the higher-priority and more frequent SPI transfers quicker access through the bridges BR3 and BR4 between SCR1 and SCR2 (section 4.2 System Interconnect Block Diagram in TRM spru77a.pdf).

The forum post http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/228396/811851.aspx#811851 discusses similar topic on SCR priority handling.

You may have already looked at the information here but if not, please go through the system interconnect details on this wiki:

http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SOC_Architecture_and_Throughput_Overview.

As you have also seen, transfer rates through the interconnect is highly dependent on the various master/slave data transfers happening in the final system implementation including the type of transfer (burst vs. non-burst). We currently do not have individual or stand-alone transfer stats for the various combinations.

Hope this helps.

Regards,

Sunil Kamath