Other Parts Discussed in Thread: TMS320DM642
I am trying to set up the McBSP on a TMS320DM642 as an SPI Master in a very simple form. I need to write 64 bits, then manually generate a pulse on the FSX pin. I don't need to do this often, nor at a high rate, so simply servicing it directly by the CPU is fine - no need to mess with interrupts or EDMA. My first attempt is to set up simply to write one 32-bit word, wait for 10 seconds, and shut down the McBSP. I would expect to see one 32-bit transfer on the scope, but I don't - I see a continual stream of 32-bti transfers, all of the correct value, that continues until the delay ends and the McBSP is closed. Why?
Here is the relevant code:
#include <stdint.h>
#include "std.h"
#include "tsk.h"
#include "csl.h"
#include "csl_mcbsp.h"
#include "biosconfigcfg.h"
MCBSP_Config testCfg =
{
MCBSP_SPCR_RMK(MCBSP_SPCR_FREE_YES, MCBSP_SPCR_SOFT_YES,
MCBSP_SPCR_FRST_NO, MCBSP_SPCR_GRST_NO,
MCBSP_SPCR_XINTM_DEFAULT, MCBSP_SPCR_XSYNCERR_DEFAULT,
MCBSP_SPCR_XRST_YES, MCBSP_SPCR_DLB_OFF,
MCBSP_SPCR_RJUST_DEFAULT, MCBSP_SPCR_CLKSTP_DELAY,
MCBSP_SPCR_DXENA_OFF, MCBSP_SPCR_RINTM_DEFAULT,
MCBSP_SPCR_RSYNCERR_DEFAULT, MCBSP_SPCR_RRST_YES), ///< spcr
MCBSP_RCR_DEFAULT, ///< rcr
MCBSP_XCR_RMK(MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(0),
MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XCOMPAND_DEFAULT,
MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_0BIT,
MCBSP_XCR_XFRLEN1_OF(0), MCBSP_XCR_XWDLEN1_32BIT,
MCBSP_XCR_XWDREVRS_DISABLE), ///< xcr
MCBSP_SRGR_RMK(MCBSP_SRGR_GSYNC_FREE, MCBSP_SRGR_CLKSP_DEFAULT,
MCBSP_SRGR_CLKSM_INTERNAL, MCBSP_SRGR_FSGM_FSG,
MCBSP_SRGR_FPER_OF(64), MCBSP_SRGR_FWID_OF(0),
MCBSP_SRGR_CLKGDV_OF(0x80)), ///< srgr
MCBSP_MCR_DEFAULT, ///< mcr
MCBSP_RCERE0_DEFAULT, ///< rcere0
MCBSP_RCERE1_DEFAULT, ///< rcere1
MCBSP_RCERE2_DEFAULT, ///< rcere2
MCBSP_RCERE3_DEFAULT, ///< rcere3
MCBSP_XCERE0_DEFAULT, ///< xcere0
MCBSP_XCERE1_DEFAULT, ///< xcere1
MCBSP_XCERE2_DEFAULT, ///< xcere2
MCBSP_XCERE3_DEFAULT, ///< xcere3
MCBSP_PCR_RMK(MCBSP_PCR_XIOEN_SP, MCBSP_PCR_RIOEN_GPIO,
MCBSP_PCR_FSXM_INTERNAL, MCBSP_PCR_FSRM_DEFAULT,
MCBSP_PCR_CLKXM_OUTPUT, MCBSP_PCR_CLKRM_OUTPUT,
MCBSP_PCR_CLKSSTAT_DEFAULT, MCBSP_PCR_DXSTAT_DEFAULT,
MCBSP_PCR_FSXP_ACTIVEHIGH, MCBSP_PCR_FSRP_DEFAULT,
MCBSP_PCR_CLKXP_RISING, MCBSP_PCR_CLKRP_DEFAULT), ///< pcr
};
void atest(void)
{
MCBSP_Handle mc = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(mc, &testCfg);
MCBSP_enableSrgr(mc);
spinDelay(100);
MCBSP_enableXmt(mc);
MCBSP_write(mc, 0x00ffff00);
TSK_sleep(10000);
MCBSP_close(mc);
while (1) {
TSK_sleep(1);
}
}
What's happening here???
Thanks!
