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about Hyperlink Throughput

kabalagala
Intellectual 300 points

Hi, Everyone!

According Hyperlink data mannual, the throughput of hyperlink should be 40gbps with 4 lanes when each of lane configured 10Gbps. 

But when i test this throughput with edma cc1 from c6670 to c6678, the result is around 20Gbps instead of 40Gbps. the configuration is  as below,

1) serdes reference clock: 250Mhz

2) pll mpy is 10x and full speed is configured, so line rate per lane is 250*40 = 10Gbps.

3) 4 lanes are actived.

3) EDMA cc1, Acnt = 31KB, Bcnt = 100.

Then i use edma move 3100KB data from c6670 to a 6678 buffer , which address is mapped into hyperlink space.

The result is thoughput of hyperlink inter-dsp ddr-to-ddr is 20.8Gbps, while throughput of intra-dsp ddr-to-ddr edma cc1 is 39Gbps.

I am confused by this result, i know in hyperlink module the 8b9b encoding and mac control header may reduce some throughput,  and it maybe

                                         40Gbps * 8/9 * 31/32 = 34.44Gbps                 (1 control packet every 32 packets.)

So, i think my result of 20.8Gbps is not correct anyway.

  • Intellectual 300 points

    In the Hyperlink user guide, Table 2-6, as below, 

     

    When RefClk = 250Mhz, MPY is 10 and Full Rate (ratescale = 0.25),  the Operating rate is x. Does this mean  the above configuration combination

    is not supported ???

  • in reply to kabalagala
    TI__Expert 4740 points

    I believe your SERDES configuration should be fine. normally, performance between DSPs are lower than lntra mode test and trace length and clock, signal quality affect the result. if you are using Molex cable and it is not hard wired, you can not expect max throughput. it will be around half in that case.

    another posibility is what kind of operation you are doing. if you are doig "READ" operation, the total performance will be around half when compared to "WRITE" performance. Read operation consumes more clock cycles for processing.

    Hope this could help.

    Albert

  • in reply to Albert Bae
    Intellectual 300 points

    Thank you Albert for your response!

     In my test, c6670 and c6678 are in the same PCB, so they are connected by hard wire instead of Molex cable, and the hard wire is very short since the two chips are near  in the same Board.

    And , I tested hyperlink write by move local buffer data to remote memory space with EDMA1, which i think, is "WRITE" operation. 

    As to the clock and signal quality, i'm not sure.

    So, Albert, i want my hyperlink to achive max throughput, can you give any advice on hardware connection, clock and signal design, and even throughput testcase?

    I checked the newest issued  TI throughput performance  user guide and didnt find any information about hyperlink.