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HyperLink interface with TI DSP Processors and FPGA's

Chris Satchell
Prodigy 60 points

I understand that the usual place to position AC coupling (or DC blocking) capacitors on a high speed serial interface is in the TX path. In fact the PCIe specification suggests these are placed in the Tx path between the PCIe serial output pins and the PCIe connector, rather than close to the Rx pin particularly for Signal Integrity considerations.

However, in TI HyperLink schematics or EVM boards the DC blocking capacitor appears to be placed nearest the Rx pin of the interface. A particular example can be seen in this EVM board schematic on p.12 where at the bottom of the page the Hyperlink schematic is drawn.

http://wfcache.advantech.com/support/6670/3/TMDXEVM6670Lx_EVM_REV_3_0_DSN.pdf

As I understand it, another purpose of the capacitor is to detect the presence of the receiver. During the initialization, the common mode voltage on the transmitter charges the capacitor. The presence or the absence of the receiver is detected using this charging time constant. This allows the transmitter to shut down if the receiver is absent because it may be on a plug-in board and it is not present. Clearly if the capacitors are nearest the Rx pins (and the board is not plugged in) this method of detection is not possible.

Is there a specific placement necessary/required for the DC blocking capacitors on a HyperLink interface - and if so please could you explain the reason. Certainly the PCIe specification dictates that the capacitors are placed close to the Tx pins.

Many thanks

Chris S.

  • 0
    TI__Genius 13475 points

    Chris

    I'm moving this post over to the Multicore DSP forum, since they are more familiar with the Hyperlink operation.

    Mark Sauerwald

     

  • 0
    TI__Mastermind 42545 points

    Hi Chris,

    The main purpose of the capacitor on the serial link is to provide an AC coupled path from the transmitter to the receiver which is biased internally.  Placement of the capacitor has more to do with the associated standard that anything else.  The placement rule ensures that the designers of the circuit at each end of the link understand where the capacitor should be located so that there is always a capacitor present. As you pointed out the PCIE standard does specify that the capacitor should be placed close to the transmitter but this appears to be the exception and not the rule.  Since the AC coupling capacitor is sometimes built into the receiver buffer the capacitor placement is often specified at the receiver to accommodate buffers with and without built in capacitors. For example the Rapid IO spec requires 'blocking capacitors in or near recievers'. We follow that convention for all the SerDes inputs on the KeyStone I devices with the exception of PCIE. You will see that the ball placement of the receiver pins allow the connection to the AC block capacitors on the top layer without any via between the capacitor and the receiver pins.  

    Since Hyperlink at 10Gbaud is only supported between two devices on the same board with up to 4" of trace, the receiver side placement may seem arbitrary but the position of the receiver balls on the outer edge of the device eliminates extra vias. 

    Regard, Bill

  • 0 in reply to Bill Taboada
    Prodigy 60 points

    Hi Bill

    Many thanks for your prompt reply and very helpful explanation. We have seen TI EVM boards that take a Hyperlink I/F over a connector - so I guess they will not be operating at 10Gbaud. As I understand it, a Hyperlink I/F can operate at several specific data rates, so my question is this - is there a full specification or document outlining the capabilities or reach of Hyperlink at its various data rates?

    Our usage will definitely require a board to board connector, but obviously it would be very useful to know what to expect as a maximum data rate.

    Kind regards

    Chris S.

  • 0 in reply to Chris Satchell
    TI__Mastermind 42545 points

    Hi Chris,

    Since the interface wasn't intended for that use it hasn't been characterized for that topology. Based on other designs we've seen a properly designed backplane with properly rated connectors should allow for performance that is similar to SRIO Gen2 at 5Gbd. You would have to simulate you connection to get any real idea of the performance you can expect.

    Regards, Bill