Hi,
I'm trying to setup splash screen support in a bootloader, in Linux it works fine. The display (640x480) is connected by parallel interface to LCD2 (dispc2_* pins).
These are the steps in chronological order how I setup the display (Display Timing Values taken from Linux):
- register initialization:
DSS_CTRL 0x48040040 0x00000000
DISPC_CONTROL2 0x48041238 0x00000308
DISPC_POL_FREQ2 0x48041408 0x00007000
DISPC_TIMING_H2 0x48041400 0x02d0115f
DISPC_TIMING_V2 0x48041404 0x02100a01
DISPC_DIVISOR2 0x4804140c 0x00010002
DISPC_SIZE_LCD2 0x480413cc 0x01df027f
DISPC_DEFAULT_COLOR2 0x480413ac 0x000000ff
DISPC_VID1_BA_0 0x480410bc 0x8d20e600
DISPC_VID1_BA_1 0x480410c0 0x8d20e600
DISPC_VID1_POSITION 0x480410c4 0x00000000
DISPC_VID1_SIZE 0x480410c8 0x01df027f
DISPC_VID1_PICTURE_SIZE 0x480410e4 0x01df027f
DISPC_VID1_ROW_INC 0x480410d8 0x00000001
DISPC_VID1_PIXEL_INC 0x480410dc 0x00000001
DISPC_VID1_PRELOAD 0x48041230 0x00000fff
DISPC_VID1_ATTRIBUTES 0x480410cc 0x42008012
DISPC_CONTROL2 0x48041238 0x00000328
- enable display:
DISPC_CONTROL2 0x48041238 0x10000329
DISPC_VID1_ATTRIBUTES 0x480410cc 0x42008013
DISPC_CONTROL2 0x48041238 0x00000329
- the DSS registers read:
DSS_SYSSTATUS 0x48040014 0x00000001
DSS_CTRL 0x48040040: 0x00000000
DSS_STATUS 0x4804005c 0x0000aaa1
CM_DSS_DSS_CLKCTRL (0x4a00 9120) reads 00000f02 (all fine).
Now the display shows a still image with random vertical stripes filling two-thirds of the display on the right side.
The other third of the display on the left side can be made to get small stripes. This is done by filling in some 0xFFs beginning at the address pointed to by DISPC_VID1_BA_0. When writing 0x99s for example the stripes are getting darker and 0x00s turn them to black. While increasing the value of DISPC_VID1_PIXEL_INC, the space between the stripes is increased too.
Do you have any idea how to solve this "only-vertical-stripes"-problem?
What bothers me is TRM Section 10.2.3 "Display Controller Integration" says in a Note below Table 10-23 (Clocks and Resets) "If video mode is used, the VPn_PCLK and VPn_CLK clocks must be generated using a CLKIN4DDR clock." How do I make sure that this is the case?
And do I need to enable the PLLs shown in Section 10.1.2.1 Figure 10-4. (DSS Clock Tree)? My assumption was that I don't need this because I'm using the "DSS_CLK selected (from PRCM)" and not the "PLL2_CLK1".
Thanks in advance
