Is it possible to split the 4 SRIO lanes on the 66AK2H12, for example, 2 going to one FPGA and 2 going to a different FPGA?
Both FPGAs will be streaming data to the DSP but not enough to justify using HyperLink. We moved to using the SRIO lanes in our design with the initial assumption that we could split the 4 lanes between the two FPGAs but now I wanted to clarify that that is even possible.
Justin
