In a nutshell we are having an issue with the DM8148 PCIe endpoint hardware, and are looking for some help. We are connecting a DM8148 to an x86 PCIe bus, and operating the DM8148 as a PCIe endpoint using the x86 PCIe as root complex and the source of the PCIe clock. Out of perhaps 10, we have a few DM8148’s that indicate PCIE_PLLSTATUS: PLL_LOCK=1 with no PCIe connection to the DM8148 (after spending some time connected to the x86 PCIe root over numerous power cycles). We’re concerned there is a DM8148 issue as PCIe link on these particular DM8148’s will not complete link training when connected to the PCIe x86 root. The DM8148 gets a capacitively coupled refclk from an IDT ICS9DBL411 PCIe differential fanout buffer, which is fed a clock from the x86 PCIe root complex. The DM8148 may receive a PCIe refclk clock before it is fully powered on. All lines are clamped to ground with RClamp0524PA. Our DM8148 uses TI PMIC TPS659113A2ZRC for power to DM8148. We verified all the power supplies are in spec and clean – especially all the 1.8V rails. We use TI8148 GP rev 2.1 silicon. ARM @ 600Mhz, DDR3 @ 400MHz. Our DM8148 board can be physically hot plugged in normal use.
On the software side we are initializing the DM8148 according to the latest EZSDK sources as a PCIe endpoint. Those sources follow the TI recommendations for endpoint initialization. Our powerup sequence allows the DM8148 to run its RBL (ROM based loader), followed by SD based u-boot MLO to initialize DDR3 and the PCIe endpoint. For good boards operating normally, the PCIe endpoint initialization sequence waits forever for the PCIe root to supply PCIe REF clk. In the u-boot MLO code, this “wait forever” in PCIe initialization waits for the PLL_LOCK bit in the PCIE_PLLSTATUS Register (offset 6EC hex) to transition from ‘0’ to ‘1’. Again this is TI supplied code.
Are there any checks we can perform here to diagnose this issue? Any experiments with PCIE_PLLCFGx register settings or other ideas?
Thanks for the help,
Jim D.
Here's the power on with full debug output from one of two DM8148's with these symptoms:
=======================No PCIe connection==========================
U-Boot 2010.06-svn25331 (Feb 28 2013 - 11:46:46)
TI8148-GP rev 2.1
ARM clk: 600MHz
DDR clk: 400MHz
DRAM: 1 GiB
MMC: OMAP SD/MMC: 0
Using default environment
In: serial
Out: serial
Err: serial
The 2nd stage U-Boot will now be auto-loaded
Please do not interrupt the countdown till TI8148_EVM prompt if 2nd stage is already flahed
Setting up pcie bus...set up wdt
pcie_disable_module()
Reset/disable PCIe.....
pcie_hw_setup()
pcie_enable_module()
Clear PCIe EP setup.....
PCIe is out reset (PRCM)
pcie_pll_setup()
begin pcie_pll_setup()...
PowerDown
SERDES config 0-4
PLL CFG0 - ENBGSC_REF
PLL CFG0 bit [4] - DIGLDO
PLL CFG0 bit [1] - ENPLLLDO
proxy TXLDO and RXLDO ena
Config multiplier
Enable PLL
(((With no PCIe connection - the MLO code should stop at the above Enable PLL polling for PLL lock=1, but these devices achieve PLL_LOCK with no PCIe connection. The working DM8148's stop here until the PCIe root supplies ref clk, the DM8148's with an issue continue here with no PCIe connection....)))
PCIe serdes and PLL setup done Successfully.....
app_retry_enable()
set_basic_config()
Status_cmd_REG @0x51001004 = 0x00100106
MSI_CAP_REG @0x51001050 = 0x00817005
enable_dbi_cs2()
set_ti81xx_device_id()
set_size_config_32()
disable_dbi_cs2()
set_bar_config_32()
config_appl_regs()
pcie_enable_link()
LTTSM enabled
PCIe D0 = 1300, D1 = 8200000
PCIe D0 = 1e00, D1 = 8200000
PCIe D0 = 7400, D1 = 8200000
PCIe D0 = 9e00, D1 = 8200000
PCIe D0 = 300, D1 = 8200000
PCIe D0 = 2900, D1 = 8200000
PCIe D0 = f000, D1 = 8200000
PCIe D0 = 3100, D1 = 8200000
PCIe D0 = 9600, D1 = 8200000
PCIe D0 = 5200, D1 = 8200000
PCIe D0 = dd00, D1 = 8200000
PCIe D0 = 6801, D1 = 8600000
PCIe D0 = 9600, D1 = 8200000
PCIe D0 = cd00, D1 = 8200000
...pages of link training dumps...
...then Watchdog reset and repeat....