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watchdog implementation 66AK2H12

Raymond Hermans
Prodigy 205 points
Other Parts Discussed in Thread: 66AK2H12

Hi,

I have some questions on the implementation of a watchdog timer for the 66AK2H12.

After studying the data manual (sprs866), TIMER64P user guide(sprugv5a) and PLL user guide (sprugv2e)
it is not fully clear how a reset is generated.

Assume the following:

- Set reset mux register -> OMODE: 101b  (Table 7-34 data manual).

- Timer16 is set up as a watchdog timer. (assumed dedicated wd timer ARM core0)

- Watchdog is enabled and put in active state.

Will this configuration trigger a device reset at timeout? (edit: this post suggests that my assumption might be right http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/254216/889847.aspx#889847)


Also are the dedicated watchdog timers only dedicated to a specific core when generating a local reset? (e.g. OMODE: 010b)

In the data manual (Table 7-34) it states that for the ARM cores the local reset output event of the RSTMUX logic is
connected to the Device Reset generation to generate reset to PLL Controller. Does this mean that there is no local reset
available for the ARM cores?

Thanks,

Raymond

  • 0
    TI__Genius 12065 points

    Raymond,

    You are right that there is no local reset from watchdog timer for the ARM cores in 66AK2H12. And Timer16 is dedicated to ARM Core0 if used as a watchdog timer.

    When OMODE=010b, for DSP CorePac, the WD timer output is routed to the local reset input of the CorePac LPSC through RSTMUX block.

    For ARM, as there is no local reset for ARM possible, the WD timer output of ARM watchdog is routed to device reset.

    When OMODE=101b, the WD timer output is routed to device reset for both DSP CorePac and ARM core.

  • 0 in reply to Steven Ji
    Prodigy 205 points

    Hi Steven,

    Thanks for the info!

    Raymond