• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 236 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EDMA optimization in PCIe

Delared Delared
Expert 1945 points

Hi,

Says that Memory write is a posted transactions and MRd is a non-posted[PCIe specification], so :

1-using CPU (32 bits): when I send data from RC to EP(shannon)  the CPU writes/read 4B by sequence don’t wait a completion TLP in MWr? and if error occured!

2- using EDMA: we have the same mechanism in MWr and MRd or there are some differences??

for e.g I want read/write a 1050B, so both in MRd and MWr I still always send 9 TLPs request? and specially in MRd I need wait a completion TLPs? Or there are some optimization added by EDMA transfer???

I need more explainations please!

  • 0
    Expert 1945 points

    Hi,

    Is there anyone that  can give me advice on the results that i had? I would really appreciate it!

  • 0
    TI__Genius 12065 points

    Delared,

    The PCIESS module itself will take care of the PCIe protocol requirement such as post/non-post transaction. It is transparent to the users.

    And there is FIFO inside the PCIESS as well, so it could control the pace of EDMA triggered transaction although EDMA is much faster than PCIe link rate. It is transparent to the users as well.

    So basically the user could just use trigger the CPU/EDMA transfer in the code without worrying about the completion TLP.

    If there is any error happens, the error will be logged in the error status registers if the error reporting capability is enabled in the PCIe configuration registers.

    Please see PCIe user guide for details.