Hi,
in PCIe user Guide, with the BAR we can specify the range [memory address] within the EP(Shannon) receive or reject the data from RC (shannon),
so says that I want send a data from RC to EP[ range 0x6000 0000 to 0x6ff0 0000]
but by mistake, I specify an address out of range so what will happen in this cases:
case 1: 0x6fe0 0000 (included in PCIe memory space, but with the data size accros that will accros the range)
case 2: 0x6ffc 0000 (included in PCIe memory space, but out of EP range)
case3: 0x7000 0002 (EMIF16 CS2 data space, supports NAND, NOR or SRAM memory)
so means that can produce a mistake config. In some register that I would not touch them or there are some protections expected (in compilation, building…)?