At the end of the following e2e post
https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/int-multi-core_dsps/f/114/t/51762.aspx
it is mentioned that "With the LSU, you must program multiple registers via the configuration bus to setup the transaction. The overhead of setting up these registers, takes more time than actually sending smaller packets, so effectively it is inserting gaps between the packets being transmitted on the pins. With larger transfers these gaps are reduced or eliminated"
How many registers are we actually talking about for C6457 (just the 5 LSU registers)? Can we get more information in the time it takes to complete setting up these registers (can be in function of CPU clocks)?
Thank you in advance.