Theoretical throughput in EDMA3 (C66x)

Delared Delared

Expert 1945 points

In “Throughput Performance Guide for C66x KeyStone Devices” [5 EDMA3 Complex Throughput]

1.   [ 5.1 Scenario 1: EDMA Transfer Between CorePac0 L2 and CorePac1 L2]It is mentioned that the theoretical throughput is equivalent to
                                 (128bits)/(8bit/byte)×(1000M/3)=5333MB/s.

I can’t understand why in this case, EDMA0 will access the CorePac0 using the DSP/3 128-bit TeraNet switch fabric similar to EDMA1 and EDMA2 ?? There are some limitation in the [hard] that I can’t use all 128-bit theraNet ?

2.   However, in other case (without L2) there are different methods to evaluate the theoretical throughput! Eg. for MSMC I found :
                             (256bits)/(8bit/byte)×(1000M/2)=16000MB/s

So why 256bits instead 128[used in L2], and 1000M divided by 2 and not 3[used in L2] ???

I need more explanations please!

over 13 years ago

0 Chad Courtney over 13 years ago

TI__Mastermind 30825 points

1.) Each CorePac is connected to the TeraNet using 128bit interface - It's connected to the 3P_A section which is CPU/3 speed. That said it can do multiple instances of this simulatenaously (with other CorePac's performing L2 - L2 transfers i.e. C0->C1, C2->C3, C4->C5, C6->C7.)

2.) MSMC is connected to TeraNet via a 256bit interface - and it's on 2A portion which operates at CPU/2. MSMC is shared across CorePac's and need to be able to support more bandwidth so it's set on this portion.

Think of it this way, you have multiple CorePac's that you're wanting to move memory between L2 of the multiple corepacs to the single MSMC. As mentioned in section 5.2 you could have 2 different transfers of L2's of different corepac's to/from MSMC and get the 2x5333MB/s, you can go up to 3 cores doing this before you start running into limitations of the MSMC interface.

Best Regards,

Chad

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Theoretical throughput in EDMA3 (C66x)