• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 97 subscribers
  • Views 474 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335xevm_sk eth0 link problem.

SANGILI KUMAR
Genius 3920 points

Hello

        We have designed device with reference of AM335xevm_sk board. we have designed with single Ethernet (RGMii1).  we didn't use RGMII2 in our design. 

      When is boot my custom device its found the eth0 PHY but its not connecting with my LAN its showing link not ready, even though i have connected the ethernet caple with my RJ-45

Here i 've attached my log:

[ 17.235229] net eth0: CPSW phy found : id is : 0x4dd074
[ 17.241455] PHY 0:01 not found
[ 17.263275] ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 23.728851] request_suspend_state: wakeup (3->0) at 23725815780 (2000-01-01 00:19:15.198441071 UTC)
[ 23.975952] init: no such service 'hciattach'
[ 24.880096] acc_open

# netcfg eth0 dhcp 

  terminated with  timeout error..

Is my PHY working fine and connection problem between PHY and RJ-45 or any other problem ?

 

  • 0
    TI__Mastermind 27890 points

    Hello Sangili,

    When you did your board layout, did you perform a timing analysis on the RGMII interface? Which PHY are you using? RGMII has very strict layout constraints due to the small timing windows presented by the interface so it is critical that a timing analysis be performed prior to committing the design to PCB.

    PHY detection and identification is done via the MDIO interface rather than the RGMII interface, so the fact that you can 'see' the PHY doesn't tell us anything about the latter interface.

  • 0 in reply to -DK-
    Genius 3920 points

    Hello DK

                 Thanks for your reply.

                 We are using same PHY (atheros) which one used in evm_sk kit so we didn't perform any test with PHY before PCB design , but we have different RJ-45 from SK kit.  our RJ-45 connecter detail is

     http://uk.farnell.com/stewart-connector/si-61001-f/magjack-rj45-gigabit-with-leds/dp/1572191 

                How to check whether the PHY is working or not.?

  • 0 in reply to SANGILI KUMAR
    TI__Mastermind 27890 points

    The RJ45 you used should be fine.

    Based on the fact that the driver is able to recognize the PHY as being attached and reports the correct PHY ID, my assumption is that the PHY is at least functional at a basic level. You can further verify this by manually accessing the PHY via the MDIOUSERACCESS1 register (TRM 14.5.10.13) or by checking that the MACCONTROL register (TRM 14.5.7.2) is reporting the current connection status correctly as these fields are (typically) updated via MDIO reads by the driver.

    Based on the information you have provided thus far, I think it likely that there exists a problem on the RGMII interface itself rather than the MDIO interface. The fact that you say no timing analysis was done prior to committing the design to PCB makes it very likely that the RGMII interface has one or more layout-induced timing violations and as such cannot successfully send or receive packets. I think the fastest way to verify this is by instrumenting the RGMII interface itself and looking for clock-to-data timing violations on both TX and RX. Depending on the results, you may be able to utilize the Atheros' ability to internally delay either TX_CLK or RX_CLK to skew your timing in the right direction. If not, a new board layout with corrected interface timing is probably your only other option if the timing on the current board is proven to be incorrect.