OMAP-L138 +1.8V power consumption in systems with no DDR

Hi,

Yes its default is VTPIO[14]=0. In order to access VTPIO register, DDR module clock needs to be provided.

Regards,

Hyun

Hello Hyun,
Thanks for your prompt answer.
May I ask you to indicate whether this problem is on a list of issues that will be fixed in the next silicion version?

Many thanks,
Milan 

Hi,

What problem are you referring to? Is there any workaround for that problem?

Regards,

Hyun

Hello Hyun,
OMAP-L138 datasheet reads as follows:

To minimize power consumption, the DDR2/mDDR controller input receivers should be placed in power-down mode by setting VTPIO[14]=1.

It looks like this bit does not default to power down mode. In order to activate power down mode, you say I have to activate DDR clock first, set VTPIO[14] to 1 and disable the module clock again.

This procedure raises questions in my team as it appears to be strange to active DDR clock wih o DDR connected.   

Questions:
1. It is not quite clear to me why the VTPIO[14] does not default to 1 upon power up. Can you please tell me whether TI is planinng to change the default state so as to minimize +1.8V power drain in systems with no DDR connected?

2. Could you please provide a full list of steps to be taken to minimize power consumption on +1.8V rail? Besides VTPIO[14], is there anything else to be done in SW?  

TI support team indicates only a leakage current of 1max mA should be observed with no DDR connected, however, the device on my prototype sinks much more. That's why I submitted my SR.

Many thanks in advance,
Milan 

Hi Milan

We have provided some additional clarifications to Guiseppe on this, hopefully he will help close on this with you.

On your questions

On 1: No there is no plan to change the default state of the register. This is tied off in design, to reflect what the power on reset default state should be. To change this requires a silicon spin and no silicon spin planned. Additionally please note that I think the default is actually as intended. Majority of the OMAPL138 customer use-case is with DDR2/mDDR , not without it. For that this is the right default setting.

On 2, I recommend following the power down sequence, provided in the mDDR/DDR2 user guide. One key step that I think you are missing is to put the PLL1 in bypass/powerdown mode.

To put the 1.8V rail in minimal IO power state, especially when not using DDR2/mDDR in your design, the recommendation would be to following the IO termination recommendation for DDR2/mDDR when un-used in the schematic checklist

http://processors.wiki.ti.com/index.php/OMAP-L13x_/_C674x_/_AM1x_Schematic_Review_Checklist#DDR2.2FmDDR_2

Disable VCLK via PSC (this is disabled by default), put PLL1 in bypass/power down state (this is also the state for the PLLs on power on reset) to reduce the MCLK to minimal (PLL1 sources the 2X_CLK/MCLK for DDR2/mDDR).

Hope this helps.

Regards

Mukul

Hello Mukul,
thank you for your thorough reply. 
I understand there is no re-spin planned.

Yet, let me make the following comments.

1.  The device defaults to DDR module clock off while leaving DDR receivers on. Not sure why.
2.  In order to set VPTIO[14] to 1, I have to turn on the DDR module clock. I suspect this may even increase the drain from +1.8V rail. Am I correct? 
3.  As much as I try I cannot find max +1.8V current required for systems with no DDR. TI support team says "only a leakage current is expected". Could you provide a numeric spec, please? 

Many thanks,
Milan

Hi Milan

Thank you for the additional background on your query. However, I think it is still not clear to me as to what is the state of PLL1 in your testing. If you do not use DDR in your design, I recommend that you keep the PLL1 in bypass/disabled mode. If you have done that, can you clarify what is the power you see on the 1.8V rails?

For 3, if you have the PLL1 enabled, for whatever reason, the way to get the power for 1.8V rail would be to use the power estimation excel spreadsheet configured to the mDDR/DDR clock to whatever is the output of PLL1_SYSCLK1 divide by 2, and keep the state enabled, and all utilization/writes etc to 0.

For 1, generally the expectation is that both the MCLK and VCLK sources for DDR are in disable or operated at bypass clock frequency (since PLLs come up default as bypass and power down). So you would see minimal power consumption from the receivers standpoint.

For 2, I understand that youa re having to enable the clocks to access the VTPIO register, but again my assumption would be that you can keep the clocks to it minimal by keeping the PLL1 in its default state.

Hope this helps

Regards

Mukul

Hello Mukul, Thanks for your thorough reply. Let me clarify.

Re 1: The device defaults DDR Clock OFF whereas DDR receivers defaults to ON. So – one part of the DDR interface defaults to no operation mode (module clock) whereas the other one defaults to operational mode (DDR receivers). This behavior does not make much sense to me, the more so that the datasheet indicates that I am supposed to reconfigure the DDR module if no DDR is connected, as shown in bullet # 2. In simple terms, I do not fully understand why SW has to disable DDR receivers in runtime. In my opinion, the device should to default to DDR receivers “disabled” upon power up. 

Re 2: Table 2-35 in the data sheet reads as follows: (1) To minimize power consumption, the DDR2/mDDR controller input receivers should be placed in power-down mode by setting VTPIO[14]=1.

Please confirm the note above speaks about +1.8V current consumption. If not, may I ask for further details? 

Re 3: The PLL1 is disabled in my prototype.

Please confirm PLL1 has NO impact on +1.8V consumption.

4. Please provide max power consumption on +1.8V rail when no DDR is connected.

I would like to know two numbers - for VTPIO[14]=0 (default) and VTPIO[14]=1 (when SW configures the DDR module as recommended). I am not going to tell you numbers I measured on my prototype. Instead, I would like you to provide the characterizaiton.

5. From Table 2-35 I take it that I have to set VTPIO[14]=1. In order to do that, DDR module clock has to be turned on.

Please consider the following scenario:
Steps:
   1. Default state upon power-up
   2. DDR Clock on
   3. Set and VTPIO[14]=1
   4. DDR Clock off

I suspect that if I turn DDR clock ON, the power consumption on +1.8V may increase as the DDR IO buffers starts operating. However, the OMAP power calculator does not indicate any power increase on +1.8V rail unless there is a trace between OMAP pins and DDR memory.

Could you please clarify whether there is  +1.8V power consumption increase when DDR module clock is on with no DDR memory connected?

As you can see, the fact that the OMAP device does not default to a minimum +1.8V current mode when no DDR is connected creates lots of questions. Sorry for that.  

Many thanks in advance,
Milan

_{Hello Mukul,
do you think you could reply to my questions above?}

_{Many thanks,
Milan}

Hi Milan

Sorry for the delay in response

Re:2: Yes I confirm that this only impacts the 1.8V current consumption

Re:3: No direct impact on 1.8V supply as PLL1 is on a 1.2V rail *however* PLL1 is also the clock source for DDR2 IO clock (you can look at the clocking section in the DDR2/mDDR chapter), so depending on your initialization, if the DDR clocks are on it can show up on 1.8V.

Re.4 To design and budget for situation/use-case that you have , where you are going through initializing the DDR clock to write to the IO PWRDN bit , I would say budget around ~25 mA worst case. The IO power will reduce the levels reported in the power appnote, when DDR is unused, properly terminated for no-use case, and input buffers are disabled.

Re:5 I hope my response on Re:4 helps. If you were to alternatively go through a proper DDR initialization sequence as documented in the DDR section etc, you will see that the power spreadsheet numbers will correlate with your findings, assuming a  finite trace length (this is just the way the IO model is created, a non zero value for trace will get you realistic numbers).

Regards

Mukul

Hi Mukul,
Thanks for your immediate reply.

Summary:
In order to reach minimum current drain on +1.8V of less than 1mA, the power supply has to be capable of 25+ miliamps minimum.

The root cause of the problem is:
1. DDR receivers default to active state.
2. VTPIO[14] can be overwritten only if DDR clock is on.

Let me raise my initial question again:
Did you add this problem to the list of issues to be solved in the next silicon version?

Also, please note that there is no info about +1.8V current in the datasheet. TI support team referred to the power calculator in the past. The fact that the chip consumes way more than it is indicated in the power spreadsheet came to light no sooner than I measured actual current on my prototype.

May I ask you to improve OMAP-L138 documentation in this respect?

Many thanks,
Milan

Hi Milan

25 mA should be max not minimum.

Milan Zelenka said:

Did you add this problem to the list of issues to be solved in the next silicon version?

There is no next silicon version planned. Based on my understanding of this issue, this will need an all layer change, and we are not planning anything that will drive an all layer change. We will add it to the lessons learnt for next generation devices.

Milan Zelenka said:

Also, please note that there is no info about +1.8V current in the datasheet. TI support team referred to the power calculator in the past. The fact that the chip consumes way more than it is indicated in the power spreadsheet came to light no sooner than I measured actual current on my prototype.

May I ask you to improve OMAP-L138 documentation in this respect?

Power Estimation spreadsheet is the way we communicate power information. There is no power information in the datasheet (no plans to put anything in the datasheet). I do think that what you hit is a corner condition, as majority of the customers for this device family always have DDR in their system, additionally a subset of the non DDR/mDDR users are at 1.8V IO.

The corrective action that I will propose will be

1) Add another foot note under Table 2-35, that provides customers a warning on what is the range of current, till VTPIO[14] is configured appropriately.

2) Add text in the Power Consumption Summary wiki to the same effect

3) Add text in the schematic checklist wiki.

Regards

Mukul