MPAX mapping not working with Hyperlink

Itai

I would like to understand better your problem. Can we schedule a call next week?

Ran

Itay,

First of all, the HyperLink data space (starting from 0x40000000) can be used as an memory endpoint directly in the local device that the local masters (CPU/EDMA) could read/write data from/to the remote device memory via the HyperLink data space. I am not sure if it is necessary to do another level of translation in the MSMC MPAX.

Regarding to the original question, could you please confirm you are using Core0 to configure and trigger EDMA for the data transfer please since you are using privid=0?

May I ask the value of "segment_size_code" in your code please? Is it possible the size segment is too large that overlaps with your source/destination setup in the EDMA param setup please? (It will be good if you could share the values of SES[0]_MPAXL/H, SES[1]_MPAXL/H after configuration setup)

Itay Chamiel said:

As a test I also tried to map to some other physical DDR address, and that did work,

Do you mean you map the DDR address (0x80000000 in your case) to some other DDR address instead of HyperLink data space, in order to verify MPAX setup please?

If the EDMA transfer is working in second case, what is the difference in the MPAX setup and EDMA src/dst setup in both cases (map to HyperLink vs map to DDR) please? 

Hi itay,

Two things:

1. hMsmc->SES_MPAX_PER_PRIVID[privid].SES[mpax_entry].MPAXL = (curr_dest >> 4) | 0x3f;

Any reasons why you are giving the shift value as 4? From section 3.5.4 in sprugw7a , I think the shift value should be given as 8. Please check with that.

2. If you are using any device master or the peripherals (eg. EDMA) to access any memory region external to the CorePac, we do have to configure the MPAX registers that are part of the MSMC controller. Any particular reason why you using the SES MPAX . Try using the SMS MPAX register than the SES.


About your second case, as Steven said, are you are mapping the DDR address to some other DDR address, in which both the addresses are physical addresses(starting from 0x80000000)?? If yes, then EDMA will have no issues in doing the transfer since both are physical addresses (not virtual).

Regards

Sud

Ran: Let's talk if the other support options don't help.

Steven:
When running an EDMA transfer such that src and dst are both explicitly set in Hyperlink space (0x40000000) the transfer works and copies memory on the other DSP's DDR memory. But I don't want to complicate my software by making it check whether it is running on DSP A or B and in case of B, map from the virtual DDR space to Hyperlink space for each transfer. I want to set up the hardware to do this for me automatically, for example I want to set up an EDMA transfer where src=0x80000000, dst=0x80000080. On DSP A it will copy from/to those actual DDR addresses, on DSP B it will actually go through Hyperlink so that both src and dst will actually be on DSP A's DDR.

I am running the test on Core 0 of DSP B. segment_size_code = 0x1a for a memory window of 128MB. The values are MPAXL = 0x0400003f, MPAXH = 0x8000001a.

In my other test case, yes, I mapped from one DDR memory space to another. I mapped 0x80000000 to 0x88000000, then performed a transfer from address 0x80000000 to 0x80000080. As expected, it actually copied data from 0x88000000 to 0x88000080. In this case MPAXL = 0x8080003f, MPAXH = 0x8000001a. (The MPAXL value makes sense because the 36-bit address of the DDR address known to the software as 0x88000000 is physically 8:08000000.)

Sudarshan:

1. The RADDR field of the SES_MPAXL register contains the upper 24 bits of a 36-bit physical address. Since my destination address is a 32-bit address I shift it right by 4. The same calculation works well for the CorePac XMC registers, whose bit fields are exactly the same.

2. As far as I can understand from sprugw7a the SMS registers are used to remap access to MSMC shared RAM (they handle access to address ranges 0x0cXXXXXX), which is irrelevant to my case.

Thanks,

-itay