Hi,
I have a question about the TMS320c6678 EVM board schematic from Advantech :
There is a nota in the page dedicated to DDR3 chips indicating that "data bits can be swapped within the bytelane to ease routing"
This could be very convenient but I am not sure this can be really done. Specially considering write leveling procedure because some DDR3 provide only one prime DQ per lane. (For example DQ0 for LSB and DQ8 for USB). This also raises the question of knowing also which is the DQ bit input that the DSP uses during write leveling.
I consider that at least prime DQ at the DDR3 side and prime DQ at the DSP side MUST remain connected together.
Here are my questions :
- During the write leveling, does the DSP use only one prime DQ input to sense the DDR3 output, or does it sense all the DQ output from the DDR3
- If only one prime DQ is sensed per lane, Which are those 8 DQ used among the 64 DQ bits?
- Do you agree that it is allowed to swap all data bits inside a bytlelane, except for the prime DQs ?
With best regards,
Bruno
