HI,
I use MCBSP+EDMA3 to transmit the on C6657 without sys/bios. In my project, I configure the register to make the MCBSP working well,but I use EDMA3 and mcbsp work together, the result is not I desire.
My mcbsp is working in slave mode, all the mcbsp clk signal is input, Frame clk = 16KHz and Bit clk = 4.096MHz. So the Mcbsp channel has 16 timeslot per frame.In my programme, I can count the 256000 times per second interrupt count in rx or tx ISR.
Because the interrupt is occur too much, then I want to use edma3 to transmit the mcbsp data. but the edma3 interrupt count is not I desire.Here is my mcbsp and edma3`s configuration.hope someone to help me find the problem.Thank you!
MCBSP configuration:
g_McbspRegCfg[MCBSP_B300].SPCR = (CSL_MCBSP_SPCR_FREE_DISABLE << CSL_MCBSP_SPCR_FREE_SHIFT)
| (CSL_MCBSP_SPCR_SOFT_DISABLE << CSL_MCBSP_SPCR_SOFT_SHIFT)
| (CSL_MCBSP_SPCR_FRST_RESET << CSL_MCBSP_SPCR_FRST_SHIFT)
| (CSL_MCBSP_SPCR_GRST_RESET << CSL_MCBSP_SPCR_GRST_SHIFT)
| (CSL_MCBSP_SPCR_XINTM_XRDY << CSL_MCBSP_SPCR_XINTM_SHIFT)
| (CSL_MCBSP_SPCR_XSYNCERR_NO << CSL_MCBSP_SPCR_XSYNCERR_SHIFT)
| (CSL_MCBSP_SPCR_XRST_DISABLE << CSL_MCBSP_SPCR_XRST_SHIFT)
| (CSL_MCBSP_SPCR_DLB_DISABLE << CSL_MCBSP_SPCR_DLB_SHIFT)
| (CSL_MCBSP_SPCR_RJUST_RZF << CSL_MCBSP_SPCR_RJUST_SHIFT)
| (CSL_MCBSP_SPCR_CLKSTP_DISABLE_00 << CSL_MCBSP_SPCR_CLKSTP_SHIFT)
| (CSL_MCBSP_SPCR_DXENA_OFF << CSL_MCBSP_SPCR_DXENA_SHIFT)
| (CSL_MCBSP_SPCR_RINTM_RRDY << CSL_MCBSP_SPCR_RINTM_SHIFT)
| (CSL_MCBSP_SPCR_RSYNCERR_NO << CSL_MCBSP_SPCR_RSYNCERR_SHIFT)
| (CSL_MCBSP_SPCR_RRST_DISABLE << CSL_MCBSP_SPCR_RRST_SHIFT);
g_McbspRegCfg[MCBSP_B300].RCR = (CSL_MCBSP_RCR_RPHASE_SINGLE_FRM << CSL_MCBSP_RCR_RPHASE_SHIFT)
| (0 << CSL_MCBSP_RCR_RFRLEN2_SHIFT)
| (CSL_MCBSP_RCR_RWDLEN2_16BIT << CSL_MCBSP_RCR_RWDLEN2_SHIFT)
| (CSL_MCBSP_RCR_RCOMPAND_MSB << CSL_MCBSP_RCR_RCOMPAND_SHIFT)
| (CSL_MCBSP_RCR_RFIG_NO << CSL_MCBSP_RCR_RFIG_SHIFT)
| (CSL_MCBSP_RCR_RDATDLY_1BIT << CSL_MCBSP_RCR_RDATDLY_SHIFT)
| (15 << CSL_MCBSP_RCR_RFRLEN1_SHIFT)
| (CSL_MCBSP_RCR_RWDLEN1_16BIT << CSL_MCBSP_RCR_RWDLEN1_SHIFT)
| (CSL_MCBSP_RCR_RWDREVRS_DISABLED << CSL_MCBSP_RCR_RWDREVRS_SHIFT);
g_McbspRegCfg[MCBSP_B300].XCR = (CSL_MCBSP_XCR_XPHASE_SINGLE_FRM << CSL_MCBSP_XCR_XPHASE_SHIFT)
| (0 << CSL_MCBSP_XCR_XFRLEN2_SHIFT)
| (CSL_MCBSP_XCR_XWDLEN2_16BIT << CSL_MCBSP_XCR_XWDLEN2_SHIFT)
| (CSL_MCBSP_XCR_XCOMPAND_MSB << CSL_MCBSP_XCR_XCOMPAND_SHIFT)
| (CSL_MCBSP_XCR_XFIG_NO << CSL_MCBSP_XCR_XFIG_SHIFT)
| (CSL_MCBSP_XCR_XDATDLY_1BIT << CSL_MCBSP_XCR_XDATDLY_SHIFT)
| (15 << CSL_MCBSP_XCR_XFRLEN1_SHIFT)
| (CSL_MCBSP_XCR_XWDLEN1_16BIT << CSL_MCBSP_XCR_XWDLEN1_SHIFT)
| (CSL_MCBSP_XCR_XWDREVRS_DISABLED << CSL_MCBSP_XCR_XWDREVRS_SHIFT);
g_McbspRegCfg[MCBSP_B300].SRGR = (CSL_MCBSP_SRGR_GSYNC_FREE << CSL_MCBSP_SRGR_GSYNC_SHIFT)
| (CSL_MCBSP_SRGR_CLKSP_RISING << CSL_MCBSP_SRGR_CLKSP_SHIFT)
| (CSL_MCBSP_SRGR_CLKSM_CLKS << CSL_MCBSP_SRGR_CLKSM_SHIFT)
| (CSL_MCBSP_SRGR_FSGM_DXR2XSR << CSL_MCBSP_SRGR_FSGM_SHIFT)
| (0 << CSL_MCBSP_SRGR_FPER_SHIFT) //If FSGM = 0, then FPER is ignored.
| (0 << CSL_MCBSP_SRGR_FWID_SHIFT)
| (0 << CSL_MCBSP_SRGR_CLKGDV_SHIFT);
g_McbspRegCfg[MCBSP_B300].MCR = (CSL_MCBSP_MCR_XMCME_2PARTITION << CSL_MCBSP_MCR_XMCME_SHIFT)
| (CSL_MCBSP_MCR_XPABLK_BLOCK0 << CSL_MCBSP_MCR_XPABLK_SHIFT)
| (CSL_MCBSP_MCR_XPBBLK_BLOCK1 << CSL_MCBSP_MCR_XPBBLK_SHIFT)
| (CSL_MCBSP_MCR_XCBLK_BLOCK0 << CSL_MCBSP_MCR_XCBLK_SHIFT)
| (CSL_MCBSP_MCR_XMCM_ENABLE << CSL_MCBSP_MCR_XMCM_SHIFT)
| (CSL_MCBSP_MCR_RMCME_2PARTITION << CSL_MCBSP_MCR_RMCME_SHIFT)
| (CSL_MCBSP_MCR_RPABLK_BLOCK0 << CSL_MCBSP_MCR_RPABLK_SHIFT)
| (CSL_MCBSP_MCR_RPBBLK_BLOCK1 << CSL_MCBSP_MCR_RPBBLK_SHIFT)
| (CSL_MCBSP_MCR_RCBLK_BLOCK0 << CSL_MCBSP_MCR_RCBLK_SHIFT)
| (CSL_MCBSP_MCR_RMCM_ENABLE << CSL_MCBSP_MCR_RMCM_SHIFT);
g_McbspRegCfg[MCBSP_B300].PCR = (CSL_MCBSP_PCR_FSXM_EXTERNAL << CSL_MCBSP_PCR_FSXM_SHIFT)
| (CSL_MCBSP_PCR_FSRM_EXTERNAL << CSL_MCBSP_PCR_FSRM_SHIFT)
| (CSL_MCBSP_PCR_CLKXM_INPUT << CSL_MCBSP_PCR_CLKXM_SHIFT)
| (CSL_MCBSP_PCR_CLKRM_INPUT << CSL_MCBSP_PCR_CLKRM_SHIFT)
| (CSL_MCBSP_PCR_SCLKME_BCLK << CSL_MCBSP_PCR_SCLKME_SHIFT)
| (CSL_MCBSP_PCR_FSXP_ACTIVEHIGH << CSL_MCBSP_PCR_FSXP_SHIFT)
| (CSL_MCBSP_PCR_FSRP_ACTIVEHIGH << CSL_MCBSP_PCR_FSRP_SHIFT)
| (CSL_MCBSP_PCR_CLKXP_RISING << CSL_MCBSP_PCR_CLKXP_SHIFT)
| (CSL_MCBSP_PCR_CLKRP_FALLING << CSL_MCBSP_PCR_CLKRP_SHIFT);
g_McbspRegCfg[MCBSP_B300].RCERE0 = 0;
g_McbspRegCfg[MCBSP_B300].RCERE1 = 0;
g_McbspRegCfg[MCBSP_B300].RCERE2 = 0;
g_McbspRegCfg[MCBSP_B300].RCERE3 = 0;
g_McbspRegCfg[MCBSP_B300].XCERE0 = 0;
g_McbspRegCfg[MCBSP_B300].XCERE1 = 0;
g_McbspRegCfg[MCBSP_B300].XCERE2 = 0;
g_McbspRegCfg[MCBSP_B300].XCERE3 = 0;
EDMA3 configuration:
gEDMACC2Regs->TPCC_DCHMAP[MCBSP0_EDMA_REVT] = (MCBSP0_EDMA_REVT << CSL_TPCC_TPCC_DCHMAP0_PAENTRY_SHIFT);
gEDMACC2Regs->TPCC_DMAQNUM[4] = (0 << CSL_TPCC_TPCC_DMAQNUM4_E36_SHIFT);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_REVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_CONST);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].SRC = (Uint32)(&g_McbspReg[ucNum]->DRR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].DST = (Uint32)(&g_usMcbsp0EdmaRxBufferPing[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_REVT + 64) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT].CCNT = 1;
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_REVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_CONST);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].SRC = (Uint32)(&g_McbspReg[ucNum]->DRR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].DST = (Uint32)(&g_usMcbsp0EdmaRxBufferPong[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_REVT + 128) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 64].CCNT = 1;
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_REVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_CONST);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].SRC = (Uint32)(&g_McbspReg[ucNum]->DRR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].DST = (Uint32)(&g_usMcbsp0EdmaRxBufferPing[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_REVT + 64) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_REVT + 128].CCNT = 1;
g_ucMcbsp0RxBufferFlag = MCBSP_BUFF_PING;
gEDMACC2Regs->TPCC_EESRH = gEDMACC2Regs->TPCC_EESRH | (1 << (MCBSP0_EDMA_REVT - 32));
gEDMACC2Regs->TPCC_IESRH = gEDMACC2Regs->TPCC_IESRH | (1 << (MCBSP0_EDMA_REVT - 32));// enable edma interrupt
//
//Mcbsp 0 Xevt
gEDMACC2Regs->TPCC_DCHMAP[MCBSP0_EDMA_XEVT] = (MCBSP0_EDMA_XEVT << CSL_TPCC_TPCC_DCHMAP37_PAENTRY_SHIFT);
gEDMACC2Regs->TPCC_DMAQNUM[4] = (0 << CSL_TPCC_TPCC_DMAQNUM4_E37_SHIFT);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_XEVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_CONST,
CSL_EDMA3_ADDRMODE_INCR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].SRC = (Uint32)(&g_usMcbsp0EdmaTxBufferPing[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].DST = (Uint32)(&g_McbspReg[ucNum]->DXR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_XEVT + 1) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT].CCNT = 1;
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_XEVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_CONST,
CSL_EDMA3_ADDRMODE_INCR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].SRC = (Uint32)(&g_usMcbsp0EdmaTxBufferPong[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].DST = (Uint32)(&g_McbspReg[ucNum]->DXR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_XEVT + 2) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 1].CCNT = 1;
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].OPT =
CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
CSL_EDMA3_TCCH_DIS,
CSL_EDMA3_ITCINT_DIS,
CSL_EDMA3_TCINT_EN,
MCBSP0_EDMA_XEVT,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_16BIT,
CSL_EDMA3_STATIC_DIS,
CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_CONST,
CSL_EDMA3_ADDRMODE_INCR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].SRC = (Uint32)(&g_usMcbsp0EdmaTxBufferPing[0]);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].DST = (Uint32)(&g_McbspReg[ucNum]->DXR);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].SRC_DST_BIDX = CSL_EDMA3_BIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].LINK_BCNTRLD = CSL_EDMA3_LINKBCNTRLD_MAKE((MCBSP0_EDMA_XEVT + 1) * 32, 1);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].SRC_DST_CIDX = CSL_EDMA3_CIDX_MAKE(0, 0);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].A_B_CNT = CSL_EDMA3_CNT_MAKE(1, 256);
gEDMACC2Regs->PARAMSET[MCBSP0_EDMA_XEVT + 2].CCNT = 1;
g_ucMcbsp0TxBufferFlag = MCBSP_BUFF_PING;
gEDMACC2Regs->TPCC_EESRH = gEDMACC2Regs->TPCC_EESRH | (1 << (MCBSP0_EDMA_XEVT - 32));
gEDMACC2Regs->TPCC_IESRH = gEDMACC2Regs->TPCC_IESRH | (1 << (MCBSP0_EDMA_XEVT - 32));// enable edma interrupt
g_ulAddress = (unsigned long)(&g_McbspReg[ucNum]->DXR);
ISR:
interrupt void McbspIsr_1( void )
{
CSL_CPINTCRegs* cpIntc0Regs = (CSL_CPINTCRegs*)CSL_CP_INTC_0_REGS;
unsigned short i;
Uint32 IPRH = 0;
// cpIntc0Regs->STATUS_CLR_INDEX_REG = CSL_INTC0_RINT1;
// g_ulMcbspIsr1Cnt++;
IPRH = gEDMACC2Regs->TPCC_IPRH;
if(IPRH & (1 << (MCBSP0_EDMA_XEVT - 32)))
{
g_ulMcbsp0XevtCnt++;
gEDMACC2Regs->TPCC_ICRH = (1 << (MCBSP0_EDMA_XEVT - 32));
}
IPRH = gEDMACC2Regs->TPCC_IPRH;
if(IPRH & (1 << (MCBSP0_EDMA_REVT - 32)))
{
g_ulMcbsp0RevtCnt++;
gEDMACC2Regs->TPCC_ICRH = (1 << (MCBSP0_EDMA_REVT - 32));
}
// else
// {
// gEDMACC2Regs->TPCC_ICRH = 0xFFFFFFFF;
// gEDMACC2Regs->TPCC_ICR = 0xFFFFFFFF;
// }
// IPRH = gEDMACC2Regs->TPCC_IPRH;
//if(IPRH)
{
// gEDMACC2Regs->TPCC_IEVAL = 1;
}
cpIntc0Regs->STATUS_CLR_INDEX_REG = CSL_INTC0_CPU_3_2_EDMACC_GINT;
}
The REVT interrupt count is 1000 per second, but the XEVT interrupt count is 0, why?