DM648 DDR2 Clock (PLL2) Issue

In the DM648 datasheet (SPRS372H), the AEA19 pin has only the function of EMIFA External Address 19.

Does the AEA19 pin have the function related to PLL2 bypass mode (DDR2 clock)?
Must the AEA19 pin be externally pulled up?

Best regards,

Daisuke

I attach a part of the documents for DM648 EVM.

Please give me an answer!

Best regards,

Daisuke

1452.DM648 EVM - Technical reference guide - DIP switches.pdf

6175.DM648 EVM - Schematic - Bootmode.pdf

If the AEA19 pin be pulled down during a power-on-reset does the PLL2 go to bypass mode?

Best regards,

Daisuke

Please try that the AEA19 pin is externally pulled down on your DM648 EVM.
For the external pull down the SW3-1 is set to OFF and a 1kΩ resistor is added.

Does not the DDR2 Memory Controller Output Clock frequency (DDR_CLKP/N) show 13.3MHz?

Best regards,

Daisuke

Daisuke,

I've found only limited information about this in the documentation.  Basically it says that it's a PLL bypass signal that is active low.  Let me see if I can find out how this is intended to be used.

Hi Ivan,

Thank you for your reply.

Can I get the documentation which you referred to?

Best regards,

Daisuke

Daisuke,

It's an internal specification document only.  I'm now checking with the original device architect on this.

Hi Ivan,

Thank you for your help.

I hope to be cleared as soon as possible.

Best regards,

Daisuke

Hi Ivan,

Has the specification about AEA19 pin been clarified?

Best regards,

Daisuke

Hi Ivan,

Have you already completed checking it?

Best regards,

Daisuke