about DDR3 configuration during boot from Emac

winston xue

Hi
       As we know,there are two areas relate DDR3 configurations
way1. The ROM code reserves the last 0xD23F bytes for this purpose in all the CorePacs.
            This area of the RAM is used to store the initial configuration of the boot process
          like the boot parameter table.

way2.We can also config the DDR3 memory controller registers,take 6614 for example,
#define CSL_BOOT_CFG_REGS (0x02620000)
#define CSL_DDR3_EMIF_CONFIG_REGS (0x21000000)

my questin is :1. About the EMAC second bootloader ,we need to config the DDR3,
can we use the way2 to config the DDR3 ?
2.Are there any details that we should take care?

here I just use the way2 to config DDR3 in my boot project

#define CSL_BOOT_CFG_REGS (0x02620000)

#define DDR_Regs ((CSL_Emif4fRegs *)CSL_DDR3_EMIF_CONFIG_REGS)
#define pllc_regs ((CSL_PllcRegs * )0x02310000)

#define CSL_DDR3_EMIF_CONFIG_REGS (0x21000000)

#define boot_cfg_regs ((CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS)

CSL_BootCfgUnlockKicker();

boot_cfg_regs->DDR3_PLL_CTL1 = 0x00000040 /*Set ENSAT bit = 1*/
|(19/2)>>8; /*BWADJ[11:8]*/

/*Set Bypass = 1*/
boot_cfg_regs->DDR3_PLL_CTL0 |= (1<<23) ;

boot_cfg_regs->DDR3_PLL_CTL1 |= 0x00002000; //Set RESET bit = 1

  boot_cfg_regs->DDR3_PLL_CTL0 = (boot_cfg_regs->DDR3_PLL_CTL0&0x00780000)|
   ((19/2)<<24)|(19<<6)|0;
  for(i=0;i<1000;i++)
   asm(" nop");            //Wait >1000ns for reset to complete

..................

  for(i=0; i< 500000; i++)
  {
  asm(" nop 5");//delay 3ms
   }
  if((0==DDR_Fill_Test(0x80000000,256, 0))
   &&(0==DDR_Fill_Test(0x80000000,256, 0xFFFFFFFF))
   &&(0==DDR_Address_Test(0x80000000,256)))
   break;
  uiRetryCount++;

Unluckly ,it the configuration can not work,but I can sure there no errors when I make the boottable,since I just successfully write the A1 register of CORE0 in the boot project.

Brs

Winston

over 12 years ago

0 ArunMani over 12 years ago

TI__Genius 9915 points

Winston,

Which device are you using?

thanks,

arun.

0 winston xue over 12 years ago in reply to ArunMani

Intellectual 555 points

Hi Arun

I am using tci6614 ,just testing EVM6614 .

Thanks

Winston

0 winston xue over 12 years ago in reply to winston xue

Intellectual 555 points

Hi Arun

Could you support me about this issue:)

Brs

Winston

0 Sudarshan R over 12 years ago in reply to winston xue

Expert 1240 points

Hi Winston,
Yes we can configure the DDR3 by programming the DDR3 memory controller registers during boot time. What seems to be the problem? Are you configuring the PLL 2 (PLL DDR3) and DDR3 EMIF properly?

You can take the GEL file of your EVM as an reference. Also try duplicating the GEL file specific to PLL and DDR3 configuration into your boot project and see if it works.

Regards

Sud

0 winston xue over 12 years ago in reply to Sudarshan R

Intellectual 555 points

Hi Sud

Yes, I config the PLL ,and the project can run successfully (I can write and read the DDR3 )when I load the .out to the EVM board from JTAG ,and I kill gel file fron ccxml .

Is there any demo project from TI ,which we can boot from EMAC and config the DDR3?

Brs

Chenguang

0 Sudarshan R over 12 years ago in reply to winston xue

Expert 1240 points

Hi Winston,
After searching through the entire ti folder I couldn't find any demo/sample project for the same. Did you try searching for any boot config related codes given by TI specific to your device?

Regards

Sud

0 ArunMani over 12 years ago in reply to Sudarshan R

TI__Genius 9915 points

Hi Winston,

6614 is not a catalog product. You need to talk to your local FAE to get the tech support on this. Having said that, we have a sample that i did for C6657 in the e2e which you can use it as reference. Remember that the DDR structure will be different for the 66145 which you can get from the tiboot.h file for 6614. Hope this helps.

Thanks,

Arun.

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about DDR3 configuration during boot from Emac