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Create SwMs instance encouter DMA problem

bing liu
Expert 2900 points

Hi,

I am working with DVRRDK3.5. I need 8 swms instances in my usecase. I modified the header file of swms link can could define 8 swms instances. Each swms instance need a swMsInstId to do the scalar job. I use the SYSTEM_SW_MS_SC_INST_SC5 and SYSTEM_SW_MS_SC_INST_VIP1_SC and set each of them to 4 swms instances as swMsInstId. The first 6 swms instances create correctly, but for the 7th one I get the following error:

[m3vpss ] 34979: SWMS: Create in progress !!!
[m3vpss ] 35020: Assertion @ Line: 148 in links_m3vpss/swMs/swMsLink_drv.c: status==FVID2_SOK : failed !!!

The error msg shows that It fails when assigning dma channel for swms instance. I find that the dma channel assigned to the first 6 swms instances is 58-63 and the max dma channel number in DVRRDK is 64. So I think it is the dma channel number is the reason why the creation fails.

So, could I increase the dma channel number? Or could I assigne the dma channel manually in order to ues the channels whose numbers is lower than 58?

Thanks in advance! Appreciate for your reply! 

  • 0
    TI__Expert 6950 points

    DMA channel allocation failure indicates a valid resource failure. You cannot eliminate this by manually assigning dma channel numbers.

    You need to design your usecase as per available resources.

  • 0 in reply to Sivagamy Govindasamy
    Expert 2900 points

    Hi Sivagamy，

    Thanks for your reply! I do need 8 swms instances in my usecase. Do you know why the dma channels assigned to swms instances start with 58? I wonder if this could be start with 56 then the channels should be enough.

  • 0 in reply to bing liu
    TI__Expert 6950 points

    Reserved channels for M3-VPSS is defined as below. Each bit corresponds to 1 channel here. That's why you are getting chan number starting from 58.

    #define UTILS_M3VPSS_EDMACH_ALLOC_0     (0x00000000)
    #define UTILS_M3VPSS_EDMACH_ALLOC_1     (0xFC000000)

    We need to analyze if some more can be alloted. Will check and let you know.

  • 0 in reply to Sivagamy Govindasamy
    Expert 2900 points

    Hi Sivagamy,

    Thanks so much! 

  • 0 in reply to bing liu
    TI__Guru 59700 points

    To open 8 swms instances you require 8 EDMA channels allocated to M3VPSS. You should ensure enableGridDraw is set to FALSE else it will require 16 EDMA channels.

    As Sivagamy mentioned the EDMA channel allocation is controlled by /dvr_rdk/mcfw/src_bios6/utils/src/utils_dma_common_cfg.c

    There is detailed documentation at the top of the file you can refer.

    For your usecase it is simplest if you swap the M3VIDEO and M3VPSS defines.In you usecase you will not be using any EDMA channels on M3VIDEO so it should be fine.

    Change

    #define UTILS_M3VPSS_EDMACH_ALLOC_0     (0x00000000)
    #define UTILS_M3VPSS_EDMACH_ALLOC_1     (0xFC000000)

    #define UTILS_M3VPSS_PARAM_ALLOC_0      (0x0000000F)
    #define UTILS_M3VPSS_PARAM_ALLOC_1      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_2      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_3      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_4      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_5      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_6      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_7      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_8      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_9      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_10     (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_11     (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_12     (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_13     (0x00000000)

    #define UTILS_M3VIDEO_EDMACH_ALLOC_0     (0xC0000000)
    #define UTILS_M3VIDEO_EDMACH_ALLOC_1     (0x030F0000)

    #define UTILS_M3VIDEO_PARAM_ALLOC_0      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_1      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_2      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_3      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_4      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_5      (0xFF000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_6      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_7      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_8      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_9      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_10     (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_11     (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_12     (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_13     (0xFFFFFFFF)

    to

    #define UTILS_M3VIDEO_EDMACH_ALLOC_0     (0x00000000)
    #define UTILS_M3VIDEO_EDMACH_ALLOC_1     (0xFC000000)

    #define UTILS_M3VIDEO_PARAM_ALLOC_0      (0x0000000F)
    #define UTILS_M3VIDEO_PARAM_ALLOC_1      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_2      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_3      (0xFFFFFFFF)
    #define UTILS_M3VIDEO_PARAM_ALLOC_4      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_5      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_6      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_7      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_8      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_9      (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_10     (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_11     (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_12     (0x00000000)
    #define UTILS_M3VIDEO_PARAM_ALLOC_13     (0x00000000)

    #define UTILS_M3VPSS_EDMACH_ALLOC_0     (0xC0000000)
    #define UTILS_M3VPSS_EDMACH_ALLOC_1     (0x030F0000)

    #define UTILS_M3VPSS_PARAM_ALLOC_0      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_1      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_2      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_3      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_4      (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_5      (0xFF000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_6      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_7      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_8      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_9      (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_10     (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_11     (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_12     (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_13     (0xFFFFFFFF)

     

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    Hi Badri,

    Glad to see you again. I think you have already knew my usecase well. I will try as you said and let you know.

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    Hi Badri,

    There is a problem. After  swapping the VIDEO and VPSS defines, the following two conflict when invoke Utils_dmaCheckClonfict(UTILS_C6XDSP_EDMACH_ALLOC_1,UTILS_M3VPSS_EDMACH_ALLOC_1,UTILS_M3VIDEO_EDMACH_ALLOC_1). Can I change one of them to avoid this error?

     #define UTILS_C6XDSP_EDMACH_ALLOC_1     (0x030F0000)   

     #define UTILS_M3VPSS_EDMACH_ALLOC_1     (0x030F0000) 

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    #define UTILS_M3VPSS_EDMACH_ALLOC_0     (0xC0000000)

    and 

    #define UTILS_C6XDSP_EDMACH_ALLOC_0     (0xFC000003) 

    also conflict.

  • 0 in reply to bing liu
    TI__Guru 59700 points

    You are right it is a conflict but it was not an issue so far since M3VIDEO was not using DMA. You can not assign any channels to M3 VIDEO and assign the previous M3VPSS configuration to DSP. So basically swap DSP and M3VPSS.

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    Hi Badri,

    Then the defines should be as follows. And we now should have 14 dma(31-26,1-0,57-56,51-48) channels for vpss. I will rebuild it and let you know.  

    #define UTILS_C6XDSP_QDMACH_ALLOC_0 (0x00000000)

    #define UTILS_C6XDSP_EDMACH_ALLOC_0 (0x00000000)
    #define UTILS_C6XDSP_EDMACH_ALLOC_1 (0xFC000000)

    #define UTILS_C6XDSP_PARAM_ALLOC_0 (0x0000000F)
    #define UTILS_C6XDSP_PARAM_ALLOC_1 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_2 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_3 (0xFFFFFFFF)
    #define UTILS_C6XDSP_PARAM_ALLOC_4 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_5 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_6 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_7 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_8 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_9 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_10 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_11 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_12 (0x00000000)
    #define UTILS_C6XDSP_PARAM_ALLOC_13 (0x00000000)

    #define UTILS_M3VPSS_QDMACH_ALLOC_0 (0x0000000F)

    #define UTILS_M3VPSS_EDMACH_ALLOC_0 (0xFC000003)
    #define UTILS_M3VPSS_EDMACH_ALLOC_1 (0x030F0000)

    #define UTILS_M3VPSS_PARAM_ALLOC_0 (0xFFFFFFF0)
    #define UTILS_M3VPSS_PARAM_ALLOC_1 (0xFFFFFFFF)
    #define UTILS_M3VPSS_PARAM_ALLOC_2 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_3 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_4 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_5 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_6 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_7 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_8 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_9 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_10 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_11 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_12 (0x00000000)
    #define UTILS_M3VPSS_PARAM_ALLOC_13 (0x00000000)

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    Hi Badri,

    Now the dma channel problem is solved. But the 7th swms instance still could not be created. It is the old problem about scaler instance. I check the 7 scaler instances supported by swms Link and find that the 1,2 and 6,7 are using the same hw, the 3 and 5 could not be used concurrently. So as you said before, the 3,4,6,7 or 4,5,6,7 should be used for the 8 swms instances. I test nearly all the combinations of these 4 scalar instances, using 2 of them each for 4 swms, using 3 of them 2 for 3 swms 1 for 2 swms, using all the 4 each for 2 swms. Any of these combinations could work. The following are some of the error massages.

    The 7th scalar is 7, the combination is 44443377

    [m3vpss ] UTILS: DMA: Allocated CH (TCC) = 30 (30)
    [m3vpss ] UTILS: DMA: 0 of 1: Allocated PaRAM = 30 (0x490043C0)
    [m3vpss ] SWMS: instance 0, sc id 7, start win 0 end win 7
    [m3vpss ] 73383: SWMS : VipScReq is FALSE!!!
    [m3vpss ] 73383: Assertion @ Line: 2196 in links_m3vpss/swMs/swMsLink_drv.c: pDrvObj->fvidHandle != NULL : failed !!!

    The 7th scalar is 3,  the combination is 44443333 (the result is the same as 44445555)

    [m3vpss ] 32463: SWMS: Create in progress !!!
    [m3vpss ] UTILS: DMA: Allocated CH (TCC) = 30 (30)
    [m3vpss ] UTILS: DMA: 0 of 1: Allocated PaRAM = 30 (0x490043C0)
    [m3vpss ] SWMS: instance 0, sc id 3, start win 0 end win 7
    [m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[32526]/CurTs[186457]
    [m3vpss ] AVSYNC:WallTime IGNORE Unexpected Discontinuity.PrevTs[186457]/CurTs[191545]
    [m3vpss ] 191545: Assertion @ Line: 2329 in links_m3vpss/swMs/swMsLink_drv.c: pDrvObj->fvidHandle != NULL : failed !!!

    The 7th scalar is 6, the combination is 44443366

    [m3vpss ] SWMS: instance 0, sc id 6, start win 0 end win 7
    [m3vpss ] 36573: SWMS : VipScReq is FALSE!!!
    [m3vpss ] 36573: Assertion @ Line: 2196 in links_m3vpss/swMs/swMsLink_drv.c: pDrvObj->fvidHandle != NULL : failed !!!

    So, I don't know what to do. But I really need 8 swms instances work concurrently in my usecase. I need your help to solve this problem.

    Thanks so much!

  • 0 in reply to Badri Narayanan
    Expert 2900 points

    Hi Badri,

    I find some defines about the scalar instance in vpsdrv_m2mScPriv.h and vps_m2mSc.h.

    #define VPS_M2M_SC_INST_MAX         (5u)

    #define VPS_M2M_SC_MAX_HANDLE       (4u)

    #define VPS_M2M_SC_MAX_CH           (64u)

    #define VPSMDRV_SC_MAX_EFF_INST         (3u)

    It is said that "All driver instance can't be opened at a time. Hence for memory allocation like descriptors, channels etc this macro is used instead of VPS_M2M_SC_INST_MAX which could be as many as different possible drivers for the same paths.When SEC0-SC5 instance is opened, only SEC1-VIP1 (SC4) could be opened."

    The above number shows that the resources are enough to create 8 scalar handles each has 8 wins. Using SC5(5) and VIP1(4), each has 4 handles should match our requirement. In my test, when using SC5 and VIP1 each assigned to 4 swms instances, the former one  could create 4 handles successfully. But the second one could just create 2 handles. So I think there must be some tricks or something we don't set properly.

  • 0 in reply to bing liu
    Prodigy 140 points
    how to solve the question? i encouter the same question.
  • 0
    Prodigy 140 points

    The error msg shows that It fails when assigning dma channel for swms instance. I find that the dma channel assigned to the first 6 swms instances is 58-63 and the max dma channel number in DVRRDK is 64. So I think it is the dma channel number is the reason why the creation fails.

    how to modify the number 58 to 30?

    thank you very much.