DDR2: Arbitrary 2X_CLK for fixed VCLK?

Hi,

We would like to ask a question on DDR2 controller of L138.

According to “7.3.2 DDR2/mDDR Memory Controller Clocking” of TRM SPRUH77,

1. VCLK is sourced from PLL0_SYSCLK2/2
2. 2X_CLK is sourced from PLL1_SYSCLK1

And it appears that the two clocks are completely INDEPENDENT. For example, if PLL0 is 300MHz so that VCLK is 150MHZ, one can program PLL1_SYSCLK1 to 264MHz, or 192MHz, or 144MHz or any arbitrary frequency as long as the clock connecting with DDR2 memory is within the memory’s datasheet specification.

Is this true?

Again according to “7.3.2 DDR2/mDDR Memory Controller Clocking” of TRM SPRUH77:

1. VCLK: clocks the command FIFO, write FIFO, and read FIFO of the DDR2/mDDR memory controller.
2. 2X_CLK : 2X_CLK clock is again divided down by 2 in the DDR PHY controller to generate a clock called MCLK.

So does there exist any relationship between the internal FIFO/mem controller clock, and the external MCLK? For a fixed VCLK, are we free to choose MCLK frequency (within legitimate range)? Does TI have any recommend ratio between VCLK and 2X_CLK?

Paul