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AM3505 - LPDDR Timing Diagrams

Mehdi Tamehi
Intellectual 450 points
Other Parts Discussed in Thread: AM3505

Are timing diagrams available to show the relationship between the LPDDR signals (CLK, DQx, DMx, DQSx, etc) and STRBENx signals?

I can’t see it in the AM3505 datasheet.

  • 0
    TI__Genius 13045 points

    TI has moved from providing timing specifications for certain high speed interfaces (like DDR) to layout specifications.  Many customers were having problems designing a robust interface through modeling using the timing specs.  This resulted in a lot of resources being used to solve the same problem over and over.  In order to make the interfaces, like LPDDR, easier to implement the strategy was implemented to provide layout specifications in the Datasheet (see sec 6.4.2).  If customers follow the layout specifications, then the LPDDR interface will work as specified.

    Regards.