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PCIe and SRIO throughput performance

Hi,

In “Throughput Performance Guide for C66x KeyStone Devices”  all PCIe and SRIO throughput performance are mentioned, and I can say about shannon:

- PCIe: the efficiency is about 128/128+24+8 =80%

- SRIO: the efficiency is about 256/(256+20) =92%

So in my case[communication between Shannons], if I want make a comparison between PCIe and SRIO I observe that SRIO should be more performant than PCIe due to Data payload size  and Overhead considerations!

May I ask there are others considerations that I should take care about in my comparison?

However, it is possible that PCIe can be better than SRIO in some cases ?! 

  • Ahh, the old which is better question :)  It really depends on the application and system connectivity needed.  Let me give you a few things to consider...

    How big is the system (number of endpoints)? SRIO scales well.

    Do you need peer-to-peer communiction? PCIe routes traffic through the RC, while SRIO is direct peer-to-peer

    Are the transactions memory mapped read/writes, or is messaging desired? Both support memory mapped, SRIO additionally supports messaging.

    Do I need address translation? Only PCIe supports within the peripheral.  You could optionally look at system level MPAX registers for translation.

    Bandwidth required? PCIe is 2 lanes 5Gbps, SRIO supports 4 lanes at 5Gbps

    Do you need to connect to an Intel host?  Backplane involved?  PCIe is the way to go for any direct connection to Intel hosts.

    I could probably go on and on, but hopefully that helps you think of some of the other system issues.

    Regards,

    Travis