C6748 LCDK EMIFA clock in GEL file

EMIFA clock = [(OSCIN) * (PLLM+1)/ (POSTDIV+1)]/ (DIV3+1) when 4.5 Divider is not used. The actual dividers and multipliers are numbers programmed in the registers plus one. With the settings in the GEL file the EMIFA clock is being set to 25Mhz [(24*25)/2]/12. Changing DIV3 to 2 should set the EMIFA clock to 100Mhz.

Please utilize the PLL calculator, we provide to program the values. subtract one from the values you program in the calculator while using the GEL file.

http://processors.wiki.ti.com/index.php/Programming_PLL_Controllers_on_OMAP-L1x8/C674x/AM18xx

Regards,

Rahul

Default 25 MHz EMIFA clock: device_PLL0(0,24,1,0,1,11,5);

Writing 3 MB to NAND took 2.6 s (I reported 3.1 s earlier, but it was with block media registration call, now I just measure Blk_Write(...))

100 MHz EMIFA clock (hopefully): device_PLL0(0,24,1,0,1,2,5);

Writing 3 MB to NAND took 1.4 s.

I also tried with GEL setting Set_Core_456MHz() which gives 38 MHz EMIFA clock and it took 1.87 s to write 3 MB to NAND.

Conclusion:

Core 300 MHz EMIFA 25 MHz: 1.15 MB/s

Core 300 MHz EMIFA 100 MHz: 2.14 MB/s

Core 456 MHz EMIFA 38 MHz: 1.6 MB/s

I am wondering if is there still something fishy. Increasing NAND clock from 25 MHz to 100 MHz makes it only 1.8 times faster. Does it make sense or not? I was actually expecting more. NAND driver uses EDMA to do transfers so I guess CPU clock would not be such a big issue.

Is this expected result?

I got more information.

As I said I am working with PSP NAND driver (C:\Program Files\Texas Instruments\pdk_C6748_2_0_0_0\biospsp_03_00_01_00\drivers\examples\evm6748\nand).

By default demo application defines clock as 100 MHz, although real clock could be something else, for example it is 25 MHz in default C6748_LCDK GEL file.

What I found out is that timing really changes if you lie to PSP driver about actual clock. So I made another run with 25 MHz clock (default GEL file)

#define NAND_CLK_FREQ               (25u * 1000u * 1000u)

And here is the snippet where this define is used.

Int32 result = IOM_EBADARGS;
PSP_nandConfig nandCfg;

nandCfg.inputClkFreq = NAND_CLK_FREQ;
nandCfg.eraseAtInit = FALSE;
/* <CAUTION>: TRUE-erases all NAND media before use! */
nandCfg.hEdma = edmaHandle;
nandCfg.nandType = PSP_NT_NAND;
nandCfg.opMode = PSP_NAND_OPMODE_DMAINTERRUPT;/*POLLED OR DMA*/
nandCfg.protectedBlocks = 50u;
nandCfg.nandDevInfo = NULL;
nandCfg.nandDevTiming = NULL;
nandCfg.edmaEvtQ = 0;
nandCfg.edmaChannel = EDMA3_DRV_DMA_CHANNEL_ANY;
nandCfg.pscPwrmEnable = FALSE;/* default no power management reqd */
nandCfg.pllDomain = PSP_NAND_PLL_DOMAIN_0;

result = PSP_nandDrvInit(&nandCfg);
if (IOM_COMPLETED != result) {
   System_printf("ERROR: PSP_nandDrvInit failed");
}

Results that I reported above all told PSP driver that clock is 100 MHz #define NAND_CLK_FREQ               (100u * 1000u * 1000u). I did couple more runs where actual clock is reported to driver.

Core 300 MHz, EMIFA 25 MHz, NAND_CLK_FREQ 25 MHz: 1.69 MB/s

Core 456 MHz, EMIFA 38 MHz, NAND_CLK_FREQ 38 MHz: 2.06 MB/s

As you can see this way results are quite a bit better. It made me even more wonder why I get such a bad result if I put EMIFA clock to 100 MHz and tell driver that it is 100 MHz. With 456/38 I got 2.06 MB/s, but with 300/100 I got 2.14 MB/s. It so tiny difference. I have to find out if I could verify those clocks with an oscilloscope. Looking at numbers, something is not quite right yet.

Andres

I can check with the PSP team regarding the performance but the performance you are seeing seems to be in line with the driver datasheet provided here:

http://processors.wiki.ti.com/index.php/OMAP-L138_Software_Design_Guide#BIOS_Drivers:

Regards,

Rahul

This is output from LCDK C6748 NAND PSP driver. Notice last line that says data bus width is 1. Should it be more like 8 or 16?

NAND_SAMPLE: Ioctl for setting nand device as RAW device is successfull

NAND_SAMPLE: Currently 2 device is set as a Raw Device
NAND_SAMPLE: Media for remote client is regsitered
NAND_SAMPLE: Block size is 2048
NAND_SAMPLE: Number of sectors in nand is 257344
NAND_SAMPLE: Is Device removable? 0
NAND_SAMPLE: No of sectors in NAND is 257344
NAND_SAMPLE: Blk/Sector size is 2048
NAND_SAMPLE: Opmode of nand is 2
NAND_SAMPLE: Vendor/Manufacturer/Maker ID of NAND device is 0x2c
NAND_SAMPLE: Device ID of the NAND device is  0xcc
NAND_SAMPLE: Size of one page is 2048
NAND_SAMPLE: Number of pages per block is 64
NAND_SAMPLE: Number of blocks in the NAND device is 4096
NAND_SAMPLE: Size of spare area of each page is  64
NAND_SAMPLE: Data bus width of the NAND device is 1