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About the AM335x PORz time after boot-up.

RY9983
Guru 10570 points

Hello,

I would like to clarify about the PORz time after boot-up.
I have refered the AM335x TRM Figure 8-18(spruh73g: P533).

There is the description that PORz have to be greater than tsx.
But, I know that the tsx is requirement of Crystal circuit.
Since the crystal circuit have been already stable after boot-up, I think it is not requirement of PORz after boot-up.

I need the MIN time of PORz after boot-up.
May I have the following answer:

 - Where is the requirement of PORz after boot-up?
 - The tsx is TYP value. After boot-up, can I think it is MIN time for PORz requirement? (Bacause the crystal circuit have been already stable.)

Best regards, RY

  • 0
    TI__Guru**** 393215 points
    What do you mean by boot-up? Normally booting commences when the device has been released from reset, sysboot values have been latched at reset rising edge, and ROM code execution begins.
     
    If you mean power-up, then I don't see any misalignment in the documents. Reset should be released after the crystal oscillator has become stable. A typical value is given for tsx, because this can vary with crystals used in custom board.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,
    Thank you for your reply.

    Biser Gatchev-XID said:
    What do you mean by boot-up?

    "After boot-up" means:
      After time that the target board was powered up and some program run.

    I would like to reset from PORz after that if any problems are occured.
    Is it allowed?
    Is the warm reset(nRESETIN_OUT) only supported after boot-up?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    I can say that manually resetting the board from PORz isn't normally practiced. This signal is usually driven by the PMIC and you should check if the PMIC (or other reset supervisor) output  that drives PORz is open-drain. Otherwise you could damage the output driver.
     
    The preferred way for manual reset is asserting nRESET_IN_OUT, as shown in the AM335X TRM, Figure 8-19.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,

    Thank you very much for let me know the important notice!
    May I have once more question about nRESET_IN_OUT time?

    How long cycles do we have to hold to low on nRESETIN_OUT pin?
    Is MIN value 30 cycle? or 50 cycle?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    Hi RY,
     
    The min. value is 30 cycles for the external warm reset. The 30-50 cycles timing on the diagram is concerning the time it takes the EMIF FIFO to be drained and DDR put in self-refresh, after which the internal chip reset is asserted. This time can't be specified precisely as it's dependent on the EMIF FIFO state at the moment.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,
    I would like to consider about this once.
    Thank you very much.
    Best regards, RY

  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,

    Thank you very much for your support.
    I talked with my customer.

    Biser Gatchev-XID said:
    I can say that manually resetting the board from PORz isn't normally practiced.

    Our customer use cold reset without using warm reset.

    The method of cold reset is driving PORz low. Is this right?
    To assert cold reset, how long should we keep low on PORz?

    Biser Gatchev-XID said:

    This signal is usually driven by the PMIC and you should check if the PMIC (or other reset supervisor) output  that drives PORz is open-drain. Otherwise you could damage the output driver.

    May I ask you about...
    Why does output driver have damage if the reset supervisor is not open-drain?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    Yes, they have to drive PORz low.
     
    As I said before, this isn't a normal practice, so there is no documentation for this timing.
     
    I don't know what is your customer's schematic, but if they use a push-pull buffer to drive PORz, and use a pushbutton to GND for manual reset, this will short the buffer's output (which is high after power-on reset), and most likely damage the buffer. That is, unless precautionary measures are taken (a serial current-limiting resistor between the buffer and pushbutton for example).
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,

    Thank you very much for your advise.
    My customer needs the timing of PORz low.
    Because, the warm reset can not reset PLLs.
    We have refered TRM Table 8-23.(spruh73g:P538)

    They are thinking the case of the system to become unstable due to noise or power flick etc..

    Could you check the timing specification of PORz low?
    Or, their development will stop.

    Best regards, RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    It was already commented that this isn't a documented way of resetting the processor, so there is no specification available. I would suggest that they try the 30 cycles that are specified for warm reset.
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points

    Biser-san,

    I understand what you say. I'm sorry to say impossible.
    I would like to be closed this matter and thank you so much for your support.

    Best regards, RY