MCSPI API

Bindu Ganesh

Expert 2220 points

Other Parts Discussed in Thread: AM3359

Hi,

1) I'm using McSPIMasterModeConfig() API

Need to know what is the importance of these modes ( Mode_0 to Mode_7) , exampe MCSPI_DATA_LINE_COMM_MODE_1

2) What is the importance of SPI channels

Regards,

Bindu

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Would you kindly inform us what software are you using?

0 Miroslav Kiradzhiyski XID over 12 years ago

TI__Mastermind 25235 points

Hi Bindu,

It would have been helpful if you had pointed out which software you are using. I suppose this is StarterWare.

The MCSPI_DATA_LINE_COMM_MODE_1-7 configs are used to set some fields in the McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF):

- Input Select (bit 18) - Reception on Data Line 0 or Data Line 1
- DPE1 (bit 17) - Transmission enable/disable for data line 1 (SPIDATAGZEN[1])
- DPE0 (bit 16) - Transmission enable/disable for data line 0 (SPIDATAGZEN[0])

For more information refer to the AM335x TRM.

You can use up to four SPI channels with the McSPI module. You can set different communication on each of these four channels.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thanx for the reply !!!

I got it cleared with MCSPI_DATA_LINE_COMM_MODE_1-7 , but

About the channels i have few doubts, like for example each indivisual slave will have 4 channels (Each channel can be set with different communication)

that is, suppose if we set

1) slave 1 with channel 1 as 8 bit

2) slave 1 with channel 2 as 16 bit

by addressing slave 1 with different channel we can use different communication , is the understanding correct about channels?

Regards,

Bindu

0 Bindu Ganesh over 12 years ago in reply to Bindu Ganesh

Expert 2220 points

Hi Miroslav,

Thanx for the reply !!!

I got it cleared with MCSPI_DATA_LINE_COMM_MODE_1-7 , but

About the channels i have few doubts, like for example each indivisual slave will have 4 channels (Each channel can be set with different communication)

that is, suppose if we set

1) slave 1 with channel 1 as 8 bit

2) slave 1 with channel 2 as 16 bit

1) by addressing slave 1 with different channel we can use different communication , is the understanding correct about channels?

2) Can I get a working code for am3359 SPI 0 , so that i can be cleared with configuring the SPI 0 Module. ( and we have ICE AM3359 board ).

Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

Bindu Ganesh said:
1) by addressing slave 1 with different channel we can use different communication , is the understanding correct about channels?

Yes, this is correct. Please read Chapter 24.3.2 McSPI Master Mode from the AM335x TRM (page 3957) where the McSPI communication channels usage is well explained.

Bindu Ganesh said:
2) Can I get a working code for am3359 SPI 0 , so that i can be cleared with configuring the SPI 0 Module. ( and we have ICE AM3359 board ).

There is an example in the StarterWare regarding McSPI usage with flash. It is located in <StarterWare_folder>/examples/evmAM335x/mcspi/mcspiFlash.c
This example, however, is for the AM335x EVM board.
The StarterWare McSPI driver is located in <StarterWare_folder>/drivers/mcspi.c

Another useful page to read: StarterWare McSPI.

You may also check the AM335x McSPI Kernel Driver's Guide.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thank you for the answer !!!

we tried to build example project mcspiFlash successfully located in startware with mcspiFlash.out located in Binary folder,but

when we programmed the ICE AM3359 board with mcspiFlash.out, we neither observe the SPI signals or UART messages (115200 Baud rate)

can you please guide what could be problem...

Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

The StarterWare example you are trying to use with the ICE board is developed for the EVM board. The EVM has a CPLD switch which you can use to set different pinmux profiles. The ICE boards does not have a CPLD switch. The StarterWare example code, however, depends on these pinmux profiles. Please check McSPIPinMuxSetup() and McSPI0CSPinMuxSetup() functions inside platform/mcspi.c. These functions are used in your example code and they utilize the EVMProfileGet() function, which most probably won't work on the ICE board. You have to modify the code and perform the pinmuxing yourself.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thank you for the reply,

Yeah, i need to modify the pinmuxing for SPI 0.

Can you please guide me how can i do these pin muxing for SPI 0, as i'm new to this am3359 processor.

Regards,

Bindu

0 Bindu Ganesh over 12 years ago in reply to Bindu Ganesh

Expert 2220 points

Hi Miroslav,

Thank you for the reply !!!

But in MCSPI.c the line Profile = EVMProfileGet() is being commented.

is it like we have to modify pinmuxing for SPI 0 ICE Board, is yes

Can you please guide me how can i do these pin muxing for SPI 0, as i'm new to this am3359 processor.

Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

The pinmuxing is a process, which enables or disables selected peripherals and outputs them to the pins of the SoC. The AM335x SoCs have many peripherals inside them but not enough pins to use them all simultaneously. This is why pinmuxing is required. Pinmuxing is actually nothing more than writing to the control registers of the different peripherals, telling the processor to enable or disable them.

In the StarterWare project, the macro HWREG provides easy hardware access.

In the McSPIPinMuxSetup() function, these lines of code are used to write to the conf_<module>_<pin> register and select McSPI pins for use:

            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_SCLK) =
                 (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                      CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D0) =
                 (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                      CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_D1) =
                 (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                      CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);
            status = TRUE;

This is from the McSPI0CSPinMuxSetup() function:

            HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI0_CS0) =
                 (CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL |
                      CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE);

Please take a look at the offset for the spi0 control registers on page 756 of the AM335x TRM.

The processor for the EVM and the ICE boards is the same, so the result of modifying these registers should always be the same.

Since you stated that you are new to this processor, I strongly suggest that you read the AM335x TRM for further information about the different control registers.

You can also read the AM335x datasheet for hardware information regarding the processor. For example the SPI0 signals are pinmuxed on the following balls on the processor:

A17 - spi0_sclk
B17 - spi0_d0
B16 - spi0_d1
A16 - spi0_cs0

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thanx for the answer !!!

I guess if i take care of the Pin muxing part in Startware example Mcspi flash

1) I should be able to observe the signals on SPI 0 module with the ICE board correct?

2) Should i even need to do the Pin muxing for UART? ( As in Starterware McSPIFlash, UART is used to put the Messages )

Thanx and Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

As I stated before, the processors on both boards are the same, so if the pinmuxing configuration is the same, then the results will be the same.

Regarding UART: The UARTStdioInit() function initializes the UART. Please use Code Composer Studio, Eclipse or a similar "intelligent" IDE to be able to track and debug your code. Using Code Composer Studio, I found that the mentioned function is a wrapper for the UARTConsoleInit() function, which configures the system clocks for UART0, then calls UARTPinMuxSetup(), which is located in platform/uart.c and selects the UART pins for use. Finally it initializes the UART for use. I noticed that UARTPinMuxSetup() uses EVMProfileGet(). Use your preferred IDE to track the code execution. This way you will gain further understanding of how StarterWare works.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thanx for the answer !!!

Below is the listed doubts, please clarify is our understanding about SPI Module correct?

1) Using McSPICSEnable(); // We will enable the SPI Module chip select

2) Using McSPICsAssert(); // we will assert the Channel number (eg 0,1,2,3) with CS

3) Using McSPICsWrite(); // we can control the SPIEn lines (Eg 0,1,2,3) connect to slave

Doubts:

1) We have to enable McSPICSEnable(), then writing to SPIEn with McSPICsWrite () will have meaning else not, is the understanding correct?

2) In am3359 TRM page # 756, what is the importance of these Conf_spi0_cs0 and Conf_spi0_cs1, i'm not clear with these configuration can you please guide me on this? and same configuration is not seen in TRM as Conf_spi1_cs0 or Conf_spi1_cs1

Thanx and regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

I'm not able to find function McSPICsWrite() in the source code.

The conf_spi0_cs0 and conf_spi0_cs1 registers are covered in section 9.3.50 conf_<module>_<pin> Register (offset = 800h–A34h) (page 811 of the TRM). This section covers a lot of registers, which names are constructed in the following manner: conf_<module>_<pin>

In your case <module> = spi0; <pin> = cs0; Therefore you have the register name conf_spi0_cs0, which is mentioned on page 756 of the TRM and there is a link to section 9.3.50, where the different register fields are described (Table 9-60). This register configures the cs0 pin of the spi0 module.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

McSPICsWrite() API, and it is not used in source code.

our doubt is, what is the use of conf_spi0_cs0 and conf_spi1_cs1

example if i'm using SPI 0, Slave 3 then which config should we use conf_spi0_cs0 and conf_spi1_cs1.

Is there any link between conf_spi0_cs0, conf_spi1_cs1 and slave select ( SPIENn)

Regards,

Bindu

0 Bindu Ganesh over 12 years ago in reply to Bindu Ganesh

Expert 2220 points

Hi Miroslav,

McSPICsWrite() API, and it is not used in source code.

Am3359 TRM page 3947, 24.1.2 it is mentioned device supports only two chip selects per module

Is this the reason that configuration is given only for conf_spi0_cs0 and conf_spi1_cs1 ( that is 2 slaves ).

If the SPI module supports only 2 slaves, can we connect more than 2 slaves using the GPIO as CS, if that is the case what is the maximum number of slaves that we can connect.

Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

Yes, section 24.1.2 mentions that only two chip selects per module are supported as the other two are not pinned out. You can see a graphics example on page 3948.

conf_spi0_cs0 and conf_spi1_cs1 are the configuration registers for two different chip select pins (pads) of two different modules - SPI0 and SPI1. I explained that in my previous post.

This means that for SPI0 module you have two chip selects SPI0_CS0 and SPI0_CS1, and two more for SPI1 module - SPI1_CS0 and SPI1_CS1.

Note that module SPI1 is never a primary function for any of the processor pins. Check section 2.3.6.5 SPI of the AM335x datasheet (page 75), where you can see which pins can be pinmuxed to module SPI1 pins in order to use this module. The configuration register for the primary function of these pins then becomes the configuration register for the corresponding SPI1 pins.

Example: You pinmux SPI1_CS0 to pin C12 of the processor, which primary function is MCASP0_AHCLKR. Then if you want to configure SPI1_CS0 pin (pad) you have to use configuration register conf_mcasp0_ahclkr.

The SPIENx lines are used to select which slave should communicate with the master. Again, please refer to the picture on page 3948 of the TRM where you can see how the SPIENx lines are outputted to SPIx_CSx pins (pads).

You can connect as many slaves as you wish using the GPIO pins of the processor. There are two limitations. One is the number of free GPIO pins (unless you use external parts). The other is the total capacitive load of all the SPI slaves connected to the SCK line, as this may lead to problems with the rise and fall time of the SCK signal. Refer to datasheets for more details.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

Thank you for the answer !!!

We have Few doubts

1) If we are using GPIO lines as chip select, then these two API's Required McSPICSEnable(); and McSPICSPolarityConfig();

2) If we set the wordlength to 24 bits using API McSPIWordLengthSet(); then placing a 32bit data into API McSPITransmitData(), will API McSPITransmitData(), will transmit only 24 bit as per my requirement and discard remaing 8 bits,

3) If API McSPITransmitData(), discard remaing 8 bits, then which will be those bits MSB or LSB

Regards,

Bindu

0 Miroslav Kiradzhiyski XID over 12 years ago in reply to Bindu Ganesh

TI__Mastermind 25235 points

Hi Bindu,

1. In your case McSPICSEnable() is not needed. The TRM states: when PIN34 field is 1 - In this mode all related option to chip select have no meaning. This also means that McSPICSPolarityConfig() is not needed and will have no effect.

2./3. Using a wordlength of 24 bits and trying to send 32 bits will result in only the most significant 24 bits being transmitted. Please refer to section 24.4.1.11 McSPI Channel (i) Transmit Register (MCSPI_TX(i)) of the TRM:

The SPI words are transferred with MSB first.

Best regards,
Miroslav

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

My requirement is to use SPI0_CS1 as GPIO line, I followed the below procedure

Working on ICE Board

1) In " ecat_appl_cnfg.h " , added { 0x0960 , 7 , AM335X_PIN_OUTPUT } in AM335X_INDCOMM_MUX iceeMux [] // Configuring the line as output

2) *((unsigned int*) 0x44E07190) = 0x00000010; // clear gpio0[4]

3) *((unsigned int*) 0x44E07194) = 0x00000010; // set gpio0[4]

Can you please guide, if I have missed out if any.....

Regards,

Bindu

0 Bindu Ganesh over 12 years ago in reply to Bindu Ganesh

Expert 2220 points

Got it .. need to set in GPIO_OE as output

0 Bindu Ganesh over 12 years ago in reply to Miroslav Kiradzhiyski XID

Expert 2220 points

Hi Miroslav,

I'm using GPIO line as Chip select, AS per my requirement i need to hold Chip select line high only after the complete transmission is done.

But the Chip select line is held high at the time of transmission, it seems that when i call API " McSPITransmitData() " it stores the transmit data to channel and will not check the transmission is completed .

Can you please guide me, how do i know that transmission data is completely transmitted, so that i can pull the CS line high.

Regards,

Bindu

Processors

Processors forum

MCSPI API