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Shared Data L2 or Shared data L3 for MSMC SRAM in C6670

Lakshmanan Kuppan
Intellectual 330 points

Dear All?

What is shared data l2 or shared data l3 in msmc sram?

-  Understood the L2 cacheability for the above two. Why splitting occurs for the MSMC SRAM?

Thanks in Advance,

K. Lakshmanan

  • 0
    TI__Guru* 84110 points

    Lakshmanan,

    If there is a specific quotation in one of the documents that has raised this concern, please let us know. It will be easier to know the exact nature of your question.

    The MSMCSRAM is shared with all four of the C66x CorePacs, and with all other bus masters in the device. The Level-2 or Level-3 designations exist for the CorePacs when they are accessing the MSMCSRAM. The base address for the MSMCSRAM is 0x0C000000. When a CorePac accesses this address, the MSMCSRAM will be treated as Shared L2, which means the Local L2 within the CorePac will not cache any of the Shared L2 MSMCSRAM but the CorePac's L1 will cache the Shared L2 MSMCSRAM.

    Using the MPAX module in a CorePac's XMC controller, you can map accesses to the MSMCSRAM to another logical address range instead of 0x0C000000. If you do that, a MAR register for that logical address will be available for you to use for controlling the cacheability of the MSMCSRAM in that new logical address range. When the MSMCSRAM is accessed in this way, through another logical address range by this MAPX mapping, it is considered to be Shared L3 memory for that CorePac, and it will be cached in Local L2 if L2 cache is configured and if the MAR register bit enables caching.

    Regards,
    RandyP