hi, Judah
it is link error, unresolved symbol "HWI_eventMap", which lib shall I link?
thanks!
on omapl138 since the watch dog is on timer1 and dspbios default clock is also timer1, how to change dspbois clock from timer1 to timer2 ? my dspbois is 5_41_03_17. thanks!
bios_L138.tci
/*
* Copyright 2010 by Texas Instruments Incorporated.
* @(#) DSP/BIOS_Kernel 5,2,5,28 02-10-2010 (cuda-u28)
*/
/*
* ======== bios_L138.tci ========
* This file contains BIOS settings for OMAPL138.
*
*/
utils.importFile("ti/bios/config/bios_6748.tci");
/*
* ======== bios.initL138 ========
* BIOS initialization for the L138 is same as for 6748 except that
* we do not reset the timer by default (timer is shared with Arm).
*/
bios.initL138 = function (prog, baseseed)
{
bios.init6748(prog, baseseed);
prog.module("CLK").RESETTIMER = false;
}
bios_6748.tci
/*
* Copyright 2010 by Texas Instruments Incorporated.
* @(#) DSP/BIOS_Kernel 5,2,5,28 02-10-2010 (cuda-u28)
*/
/*
* ======== bios_6748.tci ========
* This file contains BIOS settings for 6748.
*
*/
/*
* ======== bios.internal.setupMemory6748 ========
* This function is the top-level function that will remove all MEM segments
* from the cdb file. It will take your physical memory map from calling
* getMemoryMap() and create MEM instances in cdb.
* It will then set sections to the default segment specified and fix up
* the length and/or base of MEM segments if needed.
*/
bios.internal.setupMemory6748 = function (prog)
{
/*
* Enable the MAR bits for the entire DDR memory range.
* (0xC000 0000 - 0xDFFF FFFF)
*/
prog.module("GBL").C64PLUSCONFIGURE = 1;
prog.module("GBL").C64PLUSMAR192to223 = 0xffffffff;
/*
* BIOS MEM segments will be created from object model memory definitions.
* Place default code and data sections into specified memory segments.
*/
bios.initializeMemory(prog, "IRAM", "IRAM");
var iram = prog.module("MEM").instance("IRAM");
var l1dsram = prog.module("MEM").instance("L1DSRAM");
bios.internal.setupCache6748(prog, iram);
}
/*
* ======== bios.internal.setupCache6748 ========
*/
bios.internal.setupCache6748 = function (prog, iram)
{
var cpu = prog.cpu;
var cache_l1p = prog.module("MEM").instance("CACHE_L1P");
var l1psram = prog.module("MEM").instance("L1PSRAM");
cache_l1p.len = 0x0;
cache_l1p.base = l1psram.base + l1psram.len;
if (cpu.registers.l1PMode == undefined || cpu.registers.l1PMode == null ||
cpu.registers.l1PMode == "32k") {
if (l1psram != undefined) {
l1psram.destroy();
}
cache_l1p.base -= 0x8000;
cache_l1p.len = 0x8000;
}
else {
if (cpu.registers.l1PMode == "0k") {
l1psram.len -= 0x0;
}
else if (cpu.registers.l1PMode == "4k") {
l1psram.len -= 0x1000;
}
else if (cpu.registers.l1PMode == "8k") {
l1psram.len -= 0x2000;
}
else if (cpu.registers.l1PMode == "16k") {
l1psram.len -= 0x4000;
}
else {
throw new Error("Can't set L1P cache to size: " +
cpu.registers.l1PMode);
}
}
var cache_l1d = prog.module("MEM").instance("CACHE_L1D");
var l1dsram = prog.module("MEM").instance("L1DSRAM");
cache_l1d.len = 0x0;
cache_l1d.base = l1dsram.base + l1dsram.len;
if (cpu.registers.l1DMode == undefined || cpu.registers.l1DMode == null ||
cpu.registers.l1DMode == "32k") {
if (l1dsram != undefined) {
l1dsram.destroy();
}
cache_l1d.base -= 0x8000;
cache_l1d.len = 0x8000;
}
else {
if (cpu.registers.l1DMode == "0k") {
l1dsram.len -= 0x0;
}
else if (cpu.registers.l1DMode == "4k") {
l1dsram.len -= 0x1000;
}
else if (cpu.registers.l1DMode == "8k") {
l1dsram.len -= 0x2000;
}
else if (cpu.registers.l1DMode == "16k") {
l1dsram.len -= 0x4000;
}
else throw new Error("Can't set L1D cache to size: " +
cpu.registers.l1DMode);
}
var cache = prog.module("MEM").instance("CACHE_L2");
cache.len = 0x0;
cache.base = iram.base + iram.len;
if (cpu.registers.l2Mode != null) {
if (cpu.registers.l2Mode == "0k") {
iram.len -= 0x0;
}
else if (cpu.registers.l2Mode == "32k") {
iram.len -= 0x8000;
}
else if (cpu.registers.l2Mode == "64k") {
iram.len -= 0x10000;
}
else if (cpu.registers.l2Mode == "128k") {
iram.len -= 0x20000;
}
else if (cpu.registers.l2Mode == "256k") {
iram.len -= 0x40000;
/*
* All references to IRAM need to be changed to point to some other
* available MEM instance.
*/
var memInst = prog.module("MEM").instances();
var seg = null;
for (var i=0; i < memInst.length; i++) {
if (memInst[i].space == "code/data" && memInst[i] != iram) {
seg = memInst[i];
}
}
if (seg == null) {
throw new Error("All of IRAM is used for cache " +
"and there is no external memory in the configuration");
}
else {
bios.setMemCodeSections(prog, seg);
bios.setMemDataNoHeapSections(prog, seg);
}
iram.destroy();
}
else {
throw new Error("Can't set cache to size: " + cpu.registers.l2Mode);
}
}
}
/*
* ======== bios.init6748 ========
* BIOS initialization for the 6748
*/
bios.init6748 = function (prog, baseseed)
{
/*
* Find configuration seed files to load
*/
if (baseseed == null) {
baseseed = "ti/bios/config/cdb/c6748.cdb";
}
var seed = utils.findSeed(baseseed);
if (seed != null) {
try {
prog.load(seed);
}
catch (e) {
throw new Error ("Can't load configuration seed '" + seed + "' : "
+ e);
}
}
else {
throw new Error ("Can't find configuration seed: " + baseseed);
}
prog.module("ISRC").instance("Timer_0").iIntrSelectNum = 4;
prog.module("ISRC").instance("Timer_1").iIntrSelectNum = 40;
prog.module("HWI").instance("HWI_INT14").interruptSelectNumber = 4;
prog.module("CLK").TIMER0BASE = 0x01c20000;
prog.module("CLK").TIMER1BASE = 0x01c21000;
prog.module("CLK").TIMERSELECT = "Timer 1";
/* enable specification of Input Clock Rate */
prog.module("CLK").SPECIFYRATE = true;
prog.module("CLK").INPUTCLK = 24.0;
prog.module("CLK").RESETTIMER = true;
/* set CLKOUT to be the value of cpu.clockRate. */
bios.internal.setClkout(prog);
/* Set endian mode based on build options */
if (prog.build.target.model.endian != null) {
if (prog.build.target.model.endian != "little") {
print("Warning: '" + prog.build.target.model.endian +
"' endian mode" + " is not supported on '" +
prog.cpu.deviceName + "' device.")
}
}
prog.module("GBL").ENDIANMODE = prog.build.target.model.endian;
/* initialize the default memory segments for 6748 */
bios.internal.setupMemory6748(prog);
/* initialize some memory map registers */
bios.internal.initializeRegisterMap(prog);
}
