mac-to-mac communication on DM8168 EVM

Hi Rakesh,

Do you have the same (GMTCLK not available in absence of Ethernet cable) on the DM8168EVM base board (not daughter card)? Is it possible that your MUXMODE is changed when disconnect the cable?

Regards,

Pavel

Hi Rakesh,

Some pointers from our team - seems  PHYs are interfering: Can you please check and respond?

What guarantees that the PHY will not drive RXD, TXCLK, RXCLK RXER, COL, RXDV and TXEN?

Since this looks like a 100Mbps MAC to MAC MII connection, why the question on GMTCLK?

If connecting a cable to the RJ45 makes any difference, the Phy is not held in reset as specified in the diagram??

Best Regards

Feroz

Hi,

Initially we were thinking that MAC-to-MAC communication is not working, because GMTCLK is not available. But now we understand whole scenario.

We have given TX and RX clock to both EVMs using external crytal. Clock is of 25MHz. We have also removed PHY chip from both EVMs. In this case we are getting data on TX data line, same data is available on RX data line of opposite EVM, but opposite EVM does not reply. We are doing ping from one EVM to EVM.

So what could be the reason for above issue? Is EMAC is not understanding what it is receiving, or we need to modify EMAC driver?

Thanks

Rakesh Modi

Hi Rakesh,

Please see below inputs: Can you please try and let us know...

RX must be connected to TX in both directions. COL shouldbe tied low on both sides. 

CRS should be tied to txen. 

And you need to ensure you are running in fullduplex mode.

Best Regards

Feroz

Hi Rakesh,

Please see inputs:

It sounds like it is not hooked up correctly.

1)      Both ends of the link need to be configured for 100Mbps Full duplex. D#_ will represent Device 1 or 2

2)      D1_MCOL and D2_MCOL tied to zero

3)      D1_MCRS tied to D1_MTXEN and D2_RXDV

4)      D2_MCRS tied to D2_MTXEN and D1 RXDV

5)      D1_MTXCLK, D1_MRXCLK, D2_MTXCLK and D2_MRXCLK all tied to source Oscillator of 25Mhz

6)      D1_RXD[3:0] tied to D2_TXD[3:0]

7)      D2_RXD[3:0] tied to D1_TXD[3:0]

8)      D1_TXER tied to D2_RXER

9)      D2_TXER tied to D1_RXER

MDC and MDIO will not be used and left unconnected.

perhaps there is a LINK pin which needs to be tied high ... can you check ?

There should be no issue in either direction. Make sure you verify that the TXD and RXD busses are correctly hooked up bit 3 to 3, etc.

Best Regards

Feroz

Hi Feroz,

We have done testing in two scenario for CRS pin.

1) CRS pin tied to TXEN. In this case TXEN pin does not assert when we transmit packet.

2) CRS pin tied to high. In this case TXEN line goes high when EMAC module transmits packets. So I think we should connect CRS to 3V.

TXER pin is not available on processor, so we tied RXER pin to ground.

LINK pin is also not available on processor.

For above both the cases we found that EMAC receiver is not receiving any data. It seems that Receiver is not understanding that whether any data is available or not.

Hi Rakesh 

FYI update:

there is no link pin and there is no txer so rxer should be tied low.

BR

FEroz

Is this closed with the suggested changes? Please update us on this....

BR,

Feroz

Hi Feroz,

Thanks for your support, but we are not able to do MAC-to-MAC communication. We have decided to use switch between two processors.

Thanks

Rakesh Modi

Hi Rakesh,

Thanks for the update. SO the hardware changes alone didn't do the trick :(

Do let me know if you have any hunches/possible issues with the setup. We can get them ratified and see if we can save that extra cost..

Best Regards

Feroz

Hi Rakesh,

One more hint here if that may help...i know it may be too late....just in case...

"The only thing I can see is if the MGTCLK is also being used as a clock for the switch internals as well. MGTCLK is not required for 10/100 Mbps operation."

Best Regards

Feroz