The IFR in TMS320C6670 can not be set

Hi Armstrong ,

I too have faced the same thing. To understand better the event combiner and the interrupt mechanisms, we need to have the status of the IFR register to know which core has been interrupted. Hoping for some one to give the solution.

Regards

Sud 

 Please take a look at the INTC section, such as figure 9-1 and section 9.2.2 Event Combiner in CorePac user guide.

"Event Set Register” will set the flags of any EVT (0-127). But the “Event Flag” being set is not necessarily to trigger IFR, unless the EVT is combined in “Event Combiner” and the outputs EVT[3:0] are actively mapping to INT[15:4].

 So manually set “Event Set Register” will only trigger EVT[3:0], which COULD trigger IFR, ONLY IF EVT[3:0] are mapped to INT[15:4].

Hope it helps.

Dear Steven,

Thanks for your help.

In the user guide, it mention that "(e.g., it may be beneficial to use the event set registers to generate interrupts when testing interrupt service routines)", how to do that?

In figure 9-1, since EVT[127:4] and EVT[3:0] are connected to interrupt selector(INTMUX reg), I do not think only manually trigger EVT[3:0] can trigger IFR.

So, how to manually trigger event 127:4, so that I can get IFR set, without using EVT combiner.

Armstrong,

I think Event Set Register could be used to manually trigger the events enabled in the combiner only.

For example, if you have EVT[4] enabled in the EVT combiner and the output (either one in EVT[3:0]) is connected to INT[15:4], you could manually trigger IFR by setting bit of EVT[4] in Event Set Register.

If you have EVT[4] not enabled in combiner but directly connected to INT[15:4], you could not manually trigger the IFR by setting Event Set Register. I think only the actual system event  of EVT[4] (e.g. TETBHFULLINTn in C6670, Table 7-38 in C6670 data manual) could trigger the IFR.

Dear Steven,

I try to set IFR in follow steps:

1.Connect evm use the on board emulator, load GEL file only.

2.Check the core reg, found that INT8 in IFR is clr,also check IER, INT8 is disable(whick means DSP will not clear IFR).

3.Check EVTFLAG0, if EF0 is set, clear it for further use(strange, the EF3 always got set, even though I write to EVTCLR0 to clear it).

4.Check INTMUX2 in 0x0180_0108, map INT8 to eveent0(Use combiner EVT0, also check that no other INT use it), write 8h00 to INTSEL8 region.

5.Write 0xFFFE_FFFF to EVTMASK0 at 0x0180_0080, combine EVT16 to EVT0.

6.Write 0x0001_0000 to EVTSET0 at 0x0180_0020, manually set EVT16.

7.Check EVTFLAG0 at 0x0180_0000, EVT0 got set.

8.Check IFR, no change, INT8 in IFR is still clr.

It make me very upset.

Any suggestion?

Armstrong,

Please take a look at the following example, which is using CSL to setup the CorePac INTC for the mapping of EVT0->INT8, combining EVT16 to EVT0 and manually set EVT16.

The IFR of INT8 should be set after this setup (if you step into the code before entering into ISR, IFR bit will be automatically clear when it enters into ISR).

Hope it could help.

#include "ti/csl/csl_chip.h"
#include "ti/csl/csl_chipAux.h"
#include "ti/csl/src/intc/csl_intc.h"


#include <stdio.h>

CSL_IntcContext             intcContext;
CSL_IntcEventHandlerRecord  EventHandler[30];
CSL_IntcObj                 intcObj;
CSL_IntcHandle              hTest;
CSL_IntcGlobalEnableState   state;
CSL_IntcEventHandlerRecord  EventRecord;
CSL_IntcParam               vectId;



#define COREPAC_INTC_EVTSET0       	(*(unsigned int*)(0x01800020))
#define COREPAC_INTC_EVTMASK0		(*(unsigned int*)(0x01800080))

volatile int a = 0;

interrupt void intIsr(void)
{
	printf("enter into ISR\n");
	a = 1;

}


int main(void)
{
	int pinNum = 0;
	int bankNum = 0;

    /************************************************
     *************** INTC Configuration *************
     ************************************************/

    printf ("Debug: GEM-INTC Configuration...\n");

    /* INTC module initialization */
    intcContext.eventhandlerRecord = EventHandler;
    intcContext.numEvtEntries      = 10;
    if (CSL_intcInit(&intcContext) != CSL_SOK)
    {
        printf("Error: GEM-INTC initialization failed\n");
        return;
    }

    /* Enable NMIs */
    if (CSL_intcGlobalNmiEnable() != CSL_SOK)
    {
        printf("Error: GEM-INTC global NMI enable failed\n");
        return;
    }

    /* Enable global interrupts */
    if (CSL_intcGlobalEnable(&state) != CSL_SOK)
    {
        printf ("Error: GEM-INTC global enable failed\n");
        return;
    }

    /* Open the INTC Module for Vector ID: 8 and Event ID: 0 (combined EVT0)*/
    vectId = CSL_INTC_VECTID_8;
    hTest = CSL_intcOpen (&intcObj, 0, &vectId , NULL);
    if (hTest == NULL)
    {
        printf("Error: GEM-INTC Open failed\n");
        return;
    }


    /* Hook up ISR to interrupt */
    CSL_intcHookIsr(vectId,&intIsr);

    /* Enabling the events. */
    if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
    {
        printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n");
        return;
    }

    printf ("Debug: GEM-INTC Configuration Completed\n");


	//Init Flag
	a = 0;
	printf("a = %d\n",a);


	//Combine EVT16 to EVT0
	COREPAC_INTC_EVTMASK0 = 0xFFFEFFFF;
	//set event #16 manually
	COREPAC_INTC_EVTSET0 = 0x10000;

	// 3. Wait for entering into ISR
	while(a!=1){}


	printf("a = %d\n",a);
	printf("interrupt occurs\n");

	exit(0);
}

Dear Steven,

You are right, it  does work.

One more question.

When the program stop  at while (a != 1){}(I add a breakpoint  there), I found that the EVTFLAG0 indicate EVT0 has happened, but the IF8 does not turn to '1' immediately.

Then I click step into button, the IF8 in IFR is set(need addition cycle? I do not think the IFR need cpu intervene.).

May be this could explain why I could not use Memory Browser to get IF8 set manually.

Best regards!

Dear Steven,

Much appreciate it.