Hi all,
Recently，I am studying TILER，the document tells us the following two paragraphs.
（1）For all initiators except, HD_VPSS, the tiled space is accessed in the 512 MB address range of (6000 0000h to 7FFF FFFFh). These initiators use the access the any of 8 views by using the respective DMM_TILER_OR0 or DMM_TILER_OR1 registers.
（2）For HD_VPSS, the TILER module supports its own 4-GB virtual addressing space, from address (1 0000 0000h to 1 FFFF FFFFh), and allows any of the eight 512-MB oriented sub-spaces – or views – to be remapped in the system virtual addressing space.
I have some doubts about the above contents.
（1）For HD_VPSS（Paragraph 2）, what data in tiler sapce（6000 0000h to 7FFF FFFFh）? If I set DMM_TILER_OR0/1 registers，does it impact the data in tiler space?
（2）In HDVPSS example---m2mDeiScale（/DVRRDK_03.00.00.00/ti_tools/hdvpss/hdvpss_01_00_01_37_patched/packages/ti/psp/
examples/common/vps/m2m/m2mDeiScale），it use VpsUtils_tilerGetOriAddr（）function to achieve oriented views.
inAddrY = VpsUtils_tilerGetOriAddr(
(UInt32) appObj->inBufY[appObj->inBufIdx],
VPSUTILS_TILER_CNT_8BIT,
DEI_IN_ORI_MODE,
appObj->inWidth,
appObj->inHeight);
If I set DEI_IN_ORI_MODE as Y_Flip,that is to say 0° View with Horizontal Mirroring. It returns value is yAddr = 0x47C40020. It is a 32 bit address. Why is it a 33 bit address?? Besides, How does the DEI driver know the 33 bit address?
（3）Besides，my another thread question（http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/255575.aspx），can anyone help me?
I am looking forward to your reply. Thaks。
JQ Zhao