Hi all,
I tried to tramsfer data from SDRAM to L2 using QDMA, but it doesn't work in my application. Data transfer "from SDRAM to MSMCRAM" and "from SDRAM to SDRAM" works, but SDRAM -> L2 doesn't work. I found thread about the subject, where the same problem was discussed:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/202766.aspx
as fas as I understod a reason of the problem is in cache coherency. Author of the thread wrote that the cache writeback after initialising the buffers solves the problem. I have tried to do the same but there is no result:
Uint8 srcBuff1[512];
Uint8 dstBuff1[512];
#pragma DATA_SECTION(srcBuff1, "sdram_data");
#pragma DATA_SECTION(dstBuff1, "l2sram_data");
void main(void)
{
Uint32 i;
for (i = 0; i < 512; i++)
{
srcBuff1[i] = i/2;
dstBuff1[i] = 0;
}
CACHE_wbL2((void *)&srcBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_wbL2((void *)&dstBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_wbL1d((void *)&srcBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_wbL1d((void *)&dstBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
QDMA_Transfer();
CACHE_invL1d ((void *)&srcBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_invL2 ((void *)&srcBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_invL1d ((void *)&dstBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
CACHE_invL2 ((void *)&dstBuff1[0], sizeof(Uint8)*512, CACHE_WAIT);
...
}
Now QDMA_Transfer() in my application is completely the same as the procedure DMA_All_in_One_Transfer(void) in the thread mentioned above.
In my *.cmd file data sections are defined as:
MEMORY
{
L1D: o = 00f00000h l = 00007FFFh
L1P: o = 00e00000h l = 00007FFFh
MSMC: o = 0C000000h l = 001FFFFFh
L2SRAM: o = 00800000h l = 00080000h
SDRAM: o = 80000000h l = 20000000h
}
SECTIONS
{
sdram_data: load >> SDRAM
msmcsram_data: load >> MSMC
l2sram_data: load >> L2SRAM
}
Anyone can help me ?
