the UART TX interrupt question

Huang Derek

Intellectual 360 points

Hi TI team,

TX_FIFO consists of the transmit holding register and the transmit shift register,

so when TX_FIFO is empty, does it indicate there is no data in the transmit holding and transmit shift registers?

and when the THR interrupt is occurred,

does it indicate all data in the transmit shift register has transmitted to the direction completely or

all data in the transmit holding register has transmitted to the direction completely?

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Derek,

You can see this in AM335X TRM Table 19-11. THR empty means that last byte has been moved to shift register. This doesn't mean that the data has been completely shifted out. Bit TXSRE in the Line Status register shows if all data has been shifted out.

0 Huang Derek over 12 years ago in reply to Biser Gatchev-XID

Intellectual 360 points

Hi Biser,

in light of your explanation, when THR is empty, the THR interrupt will be occurred.

and when the transmit shift register is empty, there is no interrupt occurred.

is it right?

0 Biser Gatchev-XID over 12 years ago in reply to Huang Derek

TI__Guru**** 393215 points

Yes, if for example you want to shut down the UART after transmission, then you will have to poll the TXSRE bit in the Line Status register in order to be sure that the last byte has been transmitted before turning UART off.

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the UART TX interrupt question