AM335X PinMux Conflict

Biser,

My 512Mbytes was for future, we can start with less memory, 256Mbytes is OK.

The SPRUH73G 7.1.3.3.8.1 Chip-Select Base Address and Region Size mentions:
The GPMC 512 Mbyte address space can be divided into a maximum of seven chip-select regions with
programmable base address and programmable CS size. The CS size is programmable from 16 Mbytes
to 256 Mbytes (must be a power-of-2) and is defined by the mask field.

Does that mean the 512Mbyte space is the sum of all regions, or can we have several regions at 256Mbytes ?
Please help for correct understanding.

In 7.1.1.1 GPMC Features maximum size is 128MB, in 7.1.3.3.8.1 Chip-Select Base Address and Region Size it is 256MB
where is the truth ?

Regards,
Pousse

Biser Gatchev-XID said:

What version of the pinmux tool did you use, and what processor/package did you choose? Your dat file generates errors when trying to open it.

I have downloaded several PinMuxTool revisions:

2.5.2.0 First, but All pins are not present in the table (USB or ADC as far as I remember),
so I came back to the 2.4.1.0 which I prefer.

My file comes from this 2.4.1.0 revision.

Pousse

Pousse:

Pin Mux 2.5.2 works correctly.  There were many ball locations that were taken out of the device model that are actually not changeable.

I imported as a AM335x Rev 2.x design.  Error file is produced when you do that (attached).  These errors are expected and can be ignored.

Michael T

Also attached is the design file imported as AM335x Rev 2.x.

Do you need BOTH multiplexed gpmc_ad[15:0] AND non-multiplexed GPMC gpmc_a[25:0]?  Most all designs use one or the other.  That severely

limits the pin mux availability.   SIL REV 2.x has a few more pin mux options, but that does not help your design.  Anyweay to modify the memory GPMC req'ts?

MichaelT

Michael T said:

Also attached is the design file imported as AM335x Rev 2.x.

Do you need BOTH multiplexed gpmc_ad[15:0] AND non-multiplexed GPMC gpmc_a[25:0]?  Most all designs use one or the other.  That severely

limits the pin mux availability.   SIL REV 2.x has a few more pin mux options, but that does not help your design.  Anyweay to modify the memory GPMC req'ts?

MichaelT

Michael,
We only work with non-multiplexed memory.
Possible modification on GPMC could be to use serial Flash instead of parallel.
It will help to reduce Address number pins, but we will need an extra Serial peripheral to manage the flash.

In case of Boot on Parallel NOR memory, can we use different MUX on the address bus, or do we have to respect MUX0 or MUX1... for all pins ?

Pousse

Michael T said:

Pousse:

Pin Mux 2.5.2 works correctly.  There were many ball locations that were taken out of the device model that are actually not changeable.

Michael,
OK,
I didn't consider that it was not working properly, but as Hardware Designer, we are always more confident when we see all the pins while making the MUX plan.

Pousse

Pousse Mousse said:

Does that mean the 512Mbyte space is the sum of all regions, or can we have several regions at 256Mbytes ?
Please help for correct understanding.

In 7.1.1.1 GPMC Features maximum size is 128MB, in 7.1.3.3.8.1 Chip-Select Base Address and Region Size it is 256MB
where is the truth ?

 

512MB is the sum of all CS regions. The maximum size of a CS region is 256MB, the mention of 128MB is an error in the TRM that will be corrected in the next revision